[solved] eTimer input capture mode SPC56EL

Patriks · ‎2015-05-07

Posted on May 07, 2015 at 10:57

Hello,

I would like to use the input capture functionality of eTimer on SPC56EL. This is my eTimer configuration:


ETIMER_0.CHANNEL[0].CTRL1.B.PRISRC = 0b11000; 

ETIMER_0.CHANNEL[0].CTRL1.B.SECSRC = 0b00010; 

ETIMER_0.CHANNEL[0].CTRL1.B.CNTMODE = 0x3; 

ETIMER_0.CHANNEL[0].CTRL1.B.LENGTH = 0x0; 

ETIMER_0.CHANNEL[0].CTRL1.B.DIR = 0x0; 


ETIMER_0.CHANNEL[0].CTRL2.B.OUTMODE = 0x3; 

ETIMER_0.CHANNEL[0].CTRL2.B.OEN = 0x1; 


ETIMER_0.CHANNEL[0].CCCTRL.B.CLC2 = 0x5; 

ETIMER_0.CHANNEL[0].CCCTRL.B.CLC1 = 0x2; 

ETIMER_0.CHANNEL[0].CCCTRL.B.CMPMODE = 0x0; 

ETIMER_0.CHANNEL[0].CCCTRL.B.CPT2MODE = 0x1; 


ETIMER_0.CHANNEL[0].INTDMA.B.ICF2IE = 0x1; 

ETIMER_0.CHANNEL[0].INTDMA.B.CMPLD1DE = 0x1; 

ETIMER_0.CHANNEL[0].INTDMA.B.CMPLD2DE = 0x1; 


ETIMER_0.DREQ[0].R = DREQ_ENABLED | DREQ_CMPLD1_CH0; 

ETIMER_0.DREQ[1].R = DREQ_ENABLED | DREQ_CMPLD2_CH0;

The primary input source is the bus clock, the secondary input source is an external signal. The counter counts up with every rising edge of primary source when the secondary input is high. Additionally, I am using the compare load function to reload the compare values with DMA. Anyway, doesn´t matter because this part works fine. The counter runs up when secondary input is high and reloads the compare values. According to my configuration I expected that the eTimer captures falling edges of the secondary input source (my external signal) and stores the corresponding counter values to the CAPT_2 register. But the capture of falling edge isn´t working. Can anyone tell me if something is missing in my configuration or what I have to do to use the capture functionality? Best regards, Patrik

Erwan YVIN · ‎2015-05-29

Posted on May 29, 2015 at 14:44

Hello Patrik ,

Your configuration seems to be ok.

Did you arm the capture ?

ARM - Arm Capture

Setting this bit high starts the input capture process. This bit can be cleared at any

time to disable input capture operation. This bit is self cleared when in one shot mode

and the enabled capture circuit(s) has had a capture event(s).

1 = Input capture operation as specified by the CPT1MODE and CPT2MODE bits is

enabled.

0 = Input capture operation is disabled.

Best Regards

Erwan

View solution in original post

Erwan YVIN · ‎2015-05-29