Hello,
We are developing demo on Chorus10M using our EB's BSW stack with MCAL from ST.
We are confused about how FIFO/filtering/mailbox/buffer is working on this chip.
- In user manual, we found statement like this:
FIFOs will be assigned to CanHardwareObjects following the order of the receive objects created, i.e. FIFO0 assigned to the first receive object with elements count greater than 1, FIFO1 assigned to the second receive object with elements count greater than 1.
So it means one can controller configured in configuration tool can have up to two CanHardWareObejects with element counter greater than 1.
We tried and it is like this.
But we also found that there is a FIFO Table to configure which can be configured up to 128 items. We do not know how these tables are working together with CanHardwareObjects.
Could you help clarify to us?
and, we also find statement in Chorus_10M_RM_rev1.pdf like this:
Rx Handler: Controls the transfer of received messages from the CAN core to the
external Message RAM. The Rx Handler supports two Receive FIFOs, each of
configurable size, and up to 64 dedicated Rx Buffers for storage of all messages that
have passed acceptance filtering. A dedicated Rx Buffer, in contrast to a Receive FIFO,
is used to store only messages with a specific identifier.
So for Rx Handler the count for rx buffers are up to 64, which means two FIFOs can also just use up to 64 rx buffer while 128 FIFO table can be configured.
So, we also want to know how they work together.
Thank you so much!
Br,
Kim
