STM32 MCUs Embedded software

Edited by a ST moderator to be comliant with the ST community rules. In next time please use </> button to paste your code. Please review How to insert source code. Hi, I have a video application using F767 with LWIP and without RTOS. The custmized board has an SDRAM of 512MB. When receiving data, the pbuf.len is always 1460 bytes while the other side sends 40KB each time. Comparing to the data transfer rate can reach over 20Mbit/s, it's extremely slow in a video application, there must be fundamental issues in buffer configuration in my application. The options in lwipopts.h that I think they would be relevant to the data transfer rate are: #define MEM_ALIGNMENT 4 #define MEM_SIZE (30*1024) #define MEMP_NUM_PBUF 25 #define MEMP_NUM_UDP_PCB 4 #define MEMP_NUM_TCP_PCB 4 #define MEMP_NUM_TCP_PCB_LISTEN 2 #define MEMP_NUM_TCP_SEG 150 #define MEMP_NUM_SYS_TIMEOUT 6 #define PBUF_POOL_SIZE 20 #define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN

Hardware Platform: STM32H750XBH6Software: MDK + CubeMX FW_H7_V1.12.1github: https://github.com/Q-DEBUG/DMAMUX.gitBackground: The timers TIM12/LPTIM1/2/3 used by DMAMUX1/2 to generate synchronization/trigger signals for H7 peripherals are all 16-bit, resulting in low precision. To improve precision and facilitate jitter compensation (testing shows a deviation of approximately 0.3ms–0.5ms per second), I intend to use the internal 32-bit timer peripheral TIM2.The entire chain is divided into two parts:Part 1: DMAMUX1-CH0, using direct mode (without any synchronization signal), maps the TIM2_UP event to HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT.Part 2: DMAMUX1-CH1, using synchronization trigger mode , uses HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT as the synchronization signal to trigger UART4_TX.My current test involves modifying the original LPTIM2-triggered UART periodic output routine by changing HAL_DMAMUX1_SYNC_LPTIM2_OUT to HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT. At present, I can only observe that Ti

Hey. I'm trying to use my H7's usb interface and i've currently set it up as a cdc device.What i'm trying to implement though is the following. The stm is supposed to create a virtual connection with either a python app or a tera term terminal.Is there a function or a variable that detects if this kind of a connection is established ? For example, the pico equivalent is tud_cdc_connected() What i want to build is thiswhile(!exampleCOnnectionVariable) { HAL_DELAY(500) }Meaning that my stm would wait during initialization, until a connection is established and then proceed with the super loop.

Hi,I've implemented a USBX Audio device correctly using ThreadX and the USBX Middleware on an STM32U5 (working as a speaker).I would like now, to implement a microphone using the same USBX Middleware. For that, I would like to figure out if there are some sort of examples where the microphone is implemented (including device descriptors).I'm seeing this old conversation https://community.st.com/t5/stm32-mcus-products/usbx-mic-streaming-on-wba65/m-p/851912#M288041, but no follow-up has been provided.I don't mind an example of any other microcontroller, but I would really love to see it implemented with USBX MiddlewareThanks

Originally a comment on the How to obtain and use the STM32 96-bit UID Knowledge Base article;Moved for better discussionHello,@MCU Support TD  Can I query the following please (correct me if i'm wrong): "If you are not using HAL, then the CMSIS device header provides a definition for the address of the UID. Even without HAL, you have a uniform way to obtain the UID."uint32_t uid[3]; uid[0] = *(uint32_t *)UID_BASE; uid[1] = *(uint32_t *)(UID_BASE + 4); uid[2] = *(uint32_t *)(UID_BASE + 8); I believe this references the 0x04 and 0x08 offset from a reference manual, however this is an offset in bytes, and uid in this example is a 32bit variable.In this example are you not then offsetting by 4 times as much each time and actually missing most of the unique ID? I believe the actual code should offset by 1 32 bit object, i.e:uint32_t uid[3]; uid[0] = *(uint32_t *)UID_BASE; uid[1] = *(uint32_t *)(UID_BASE + 1); uid[2] = *(uint32_t *)(UID_BASE + 2); 

I’m trying to build a UAC2.0 (USB Audio Class 2.0) device on STM32H7, supporting: High-Speed USB 24-bit audio Playback + Recording Full-duplex, stable, low-latency operation After reviewing many threads here, I still haven’t found a complete or working reference. Previous Threads Don’t Answer the Core Question Here are some related ST Community posts with no clear resolution: Using STM32H7 SAI Slave Mode for USB Audio (UAC2.0) with DSD Format - no reply Getting TinyUSB UAC2.0 Multi-Channel Audio Working on STM32H7S78-DK High-Speed Port - TinyUSB marked as unsupported, redirected to X-CUBE-AUDIO X-CUBE-AUDIO: USB audio high speed not work with iOS - still unresolved. USB Audio Device/Host Class 2.0 Middleware support? - response was to use X-CUBE-AUDIO or USBX Across all of these, the same question remains unanswered: Is there a working UAC2.0 reference for STM32H7?   What I Have Tried (and Why I’m Stuck) 1. X-CUBE-AUDIO-KIT Not to be confused with X-CUBE-AU

Hello Everyone, Since the STM32CubeMX .ioc file does not exist for the DAC_GenerateWaveform_TriggerHW example code (as usual), does anyone have suggestions/recommendations on the best way to recreate it? Seems like I need to make iterative guesses in STM32CubeMX and then see if the numbers start matching up in the original DAC_GenerateWaveform_TriggerHW example code? Thanks! C:\ST\STM32Cube_FW_H7_V1.12.1\Projects\NUCLEO-H7A3ZI-Q\Examples_LL\DAC\DAC_GenerateWaveform_TriggerHW\Src\main.c 

Hello!I have an MQTT project using NetX Duo, which publishes MQTT messages to a remote server. But, before it can do that, a secure connection must be established using TLS v1.2, which takes about 18-20 seconds (checked while debugging and stepping through the connect function). So, I wanted to find a way to make that process faster.I found this post on the forums, here (porting Mbed TLS to the STM32H5 platform with hardware crypto acceleration). But this raised some questions for me. Firstly, how to exactly implement this in the NetX Duo's TLS setup (if even possible)? And secondly, I am missing the AES option in the CubeMX settings - is that correct or I am missing something? I only have PKA, HASH, RNG and GTZC options.I checked the included files in the above linked post on how to port the mbedTLS, but was a bit overwhelmed as how would one implement it into the NetX Duo's TLS connection setup. I am using an RSA key(s) for the secure connection. I was hoping that someone might

Hello there,as wolfssl_connect is not getting out any ClientHello, I was wondering if it is due to the change of the memory?I am using an example as starting point. Unfortunately it is coming only with the fsbl.ld, so I made changes, so it access the main RAM:/* ****************************************************************************** ** ** @file : STM32N6XX_AXISRAM2_fsbl.ld ** ** @author : GPM Application Team ** ** @brief : Linker script for STM32N6XX Device from STM32N6 series ** 2048 KBytes RAM ** ** Set heap size, stack size and stack location according ** to application requirements. ** ** Set memory bank area and size if external memory is used ** ** Target : STMicroelectronics STM32 ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ****************************************************************************** ** @attention ** ** Copyright (c) 2024 STMicroelectronics. ** All rights reserved. ** ** This software is licensed under term

Hi,We are using a custom board based on STM32U5G7VJTxQ and implementing USB Mass Storage Class (USBX) to expose an SD card formatted with a file system created using FileX.The SD card when formatted with FAT32 (using FileX API), the USB mass storage device takes a very long time to become available on Windows.Observed behavior:As soon as the USB cable is plugged in, Windows shows a pop-up message:"Please insert a disk into USB drive"After approximately 3-4 minutes, the drive finally appears automatically and becomes accessible.Once the drive is mounted, it works normally.We would like to understand:What could cause this very slow enumeration/access time with FAT32?Are there any known limitations or required configurations in USBX + FileX when using FAT32?Could this be related to SD card access speed, cluster size, cache configuration, or USB MSC parameters?Are we missing any required FileX, USBX, or HAL configurations specific to FAT32?Any guidance or suggestions would be appreciated.T

Hello,In a typical example, there is the following linker script: /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ : : ._user_heap_stack : { . = ALIGN(8); PROVIDE ( end = . ); PROVIDE ( _end = . ); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); } >RAM  On paper, the intention is the stack has an allocation of _Min_Stack_Size (0x400) bytes. So far so good.However, the location _Min_Stack_Size seems to have nothing to do with _estack which the is actual address assigned to the MSP by the start-up code.The map file shows that "stack" is located between 0x20000208 and 0x20000608. ._user_heap_stack 0x0000000020000004 0x604 load address 0x0000000008000c5c 0x0000000020000008 . = ALIGN (0x8) *fill* 0x0000000020000004 0x4 [!provide] PROVIDE (end = .) 0x000000002000

Hi, I designed a board with a STM32U535 that connects to a USB host. I wanted to perform my production programming by doing the first flash over USB, without any test jig to pull-up/down any pin. But I've just realized in AN2606, that, from my understanding:- The U535 devices uses Pattern 12 to enter the bootloader- The pattern 12 doesn't have "main flash empty" condition like most other patterns/families.In this pattern 12, I see lots of conditions that I don't really understand (especially the ones with NSBOOTADD0, reference that is not documented anywhere else in this document).Is there a way to enter the bootloader by using only the USB connection, without actively forcing BOOT0 to 1 ? 

Hello,I would like to calculate a CRC-16/IBM-SDLC.I configure the CRC_HandleTypeDef structure as below for HAL_CRC_Init function:h->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE;h->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE;h->Init.GeneratingPolynomial = 0x00001021U;h->Init.CRCLength = CRC_POLYLENGTH_16B;h->Init.InitValue = 0x0000FFFFU;h->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE;h->Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_ENABLE;h->InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;But it seems that the parameters 'InputDataInversionMode' and 'OutputDataInversionMode' have no effect because I get 0xA60C as result for input 0x11 0x22 0x33 0x44 what it is matching with CRC-16/GENIBUS.Someone could be help me to understand the issue?

Hello ST!This is a bug report of sorts, since the `UTIL_SEQ_Run()` function is still marked that it allows nested calls. (I'm looking into the sequencer as delivered with the WBA package.)In the past two years, somebody had introduced an obvious error into `UTIL_SEQ_Run()` function (when they were adding the support for the `UTIL_SEQ_PostTask()` or the `TaskClearList` feature.)Inside the call to `TaskCb` callback, the static variable `CurrentTaskIdx` would be changed by the nested `UTIL_SEQ_Run()` call. Yet, after return from the callback, the variable (now with incorrect value) is used twice (before being set to `UTIL_SEQ_NOTASKRUNNING`). Two years ago when I was reviewing the code for the first time, and the bug wasn't there. (Indeed, the sequencer included with the early versions of STM32CubeWBA package has correct implementation of UTIL_SEQ_Run() that handles the nested calls correctly.) The old version of sequencer from WBA FW package v1.0.0https://github.com/STMicr

I get two errors from here:ret = wolfSSL_connect(g_tls.ssl);if (ret == WOLFSSL_SUCCESS) {printf("TLS handshake OK\r\n");g_tls.state = TLS_STATE_TLS_ESTABLISHED;} else{int err = wolfSSL_get_error(g_tls.ssl, ret);if (err == WOLFSSL_ERROR_WANT_READ ||err == WOLFSSL_ERROR_WANT_WRITE) {} else {printf("TLS handshake failed: %d\r\n", err);g_tls.state = TLS_STATE_ERROR;ret = -1 and err = 32No ClientHello is being sent.This is how the main looks:/* USER CODE BEGIN Header *//********************************************************************************* @file : main.c* @brief : Main program body******************************************************************************* @attention** Copyright (c) 2024 STMicroelectronics.* All rights reserved.** This software is licensed under terms that can be found in the LICENSE file* in the root directory of this software component.* If no LICENSE file comes with this software, it is provided AS-IS.********************************************************

Hello, Does the stm32n6570-dk has no support for lwip?

Hello everyone,I wanted to ask you about a problem we are having with the combination of the STM32H7 chip and a 16-bit SDRAM memory, AS4C16M16SA.To give you some context, we are reading data from a sensor, a radar, which generates 18432 bytes per frame, and we have 47 frames. So, in each frame, we receive an IRQ and we start the process of reading the data via SPI and DMA. When the DMA has finished copying all the data to an external RAM buffer, we do a memcpy to a larger buffer (in the SDRAM) that collects all the frames.Then, once we have these 47 frames in the SDRAM, we simply copy them to the eMMC memory (configured as a FatFS) with the f_write command.This is where the problem arises: the data we get is not what we expected. Since it is radar data, we have an algorithm that returns images, and they do not match what we should be getting. The key is that we have the same system but with 8-bit data memory, and with this, the data we get is what we expected. The question is, is

Hi,I have been using OpenAMP on an STM32H755ZIT MCU recently but ran into an issue where the mcu would go into hard fault caused by a bus fault somewhere in virtio code. The issue occurs only after a while, after dozens of messages have successfully been passed in both directions.I haven't been able to exactly pinpoint the violation because i get an IMPRECISERR bus error and have not been able to disable write buffering (I tried with an MPU config which failed and the config register value from https://community.st.com/t5/stm32-mcus/how-to-debug-a-hardfault-on-an-arm-cortex-m-stm32/ta-p/672235, but that doesn't seem to exist on this mcu). I did seem to get the rough area of the fault with the stack trace which pointed me to `uint16_t vq_ring_add_buffer`. Because of the disassembly view and register state before the fault I think the error relates to a str in the 0x20010000-0x2001ffff memory region which is the DTCM memory region of the CM7 core according to the datasheet. This doe

STMicroelectronics Support Team,I am currently working on a project using the ST67W611M1 Wi-Fi module and I would like to request your technical support regarding a platform migration.I have successfully validated the ST67W611M1 using the STM32U575ZI-Q Nucleo board, running the test and reference applications provided in X-CUBE-ST67W61.With this setup, the NCP firmware, AT command interface, and Wi-Fi connectivity are all working as expected.My objective is now to migrate this implementation from the STM32U575ZI-Q (STM32U5 series) to an STM32G0B1RE, which will be the target MCU for the final product.Given the architectural differences between the STM32U5 and STM32G0 families (clock tree, peripherals, HAL configuration, and BSP adaptations), I would appreciate your guidance on the following points:Recommended procedure or reference examples for migrating the ST67W611M1 host firmware from STM32U5 to STM32G0Any known limitations or constraints when using the ST67W611M1 with the STM32G0 se

Hi, in STM32H7 dual core, i have an example of data sharing between the core using ring buffer method, here when caches are enabled, the data sharing is not happening what will be the reason. when caches enabling lines are disabled data sharing is happening.  ring buffer is placed in D3 SRAM        regards. Srinath

Post edited by ST moderator to be inline with the community rules for the code sharing. In next time please use </> button to paste your code and a linker script content. Please read this post: How to insert source code. Hello,I'm trying to use an LCD with ILI9341 chip. I've connected all pins to the LCD and I've set in CubeMX the FMC like this: But when I tried to run the program, all calls from main.c is calling MX_FMC_Init(); then is going in this function: HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, const FMC_NORSRAM_InitTypeDef *Init) { .. __FMC_NORSRAM_DISABLE(Device, Init->NSBank); .. And soon this macro is executed function MemManage_Handler() is called: /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ SerialPrint("MemManager_Handler fault.."); /* USER CODE END MemoryManagement_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ /* U

I’m working on a project using STM32H7 (Cortex-M7 core) with eMMC and Azure RTOS FileX to manage file systems.The buffer is allocated as:ALIGN_32BYTES (uint32_t fx_mmc_media_memory[FX_STM32_MMC_DEFAULT_SECTOR_SIZE / sizeof(uint32_t)]);During initialization, I call:fx_system_initialize();fx_media_open(&gst_mmc_disk, "eMMC", fx_stm32_mmc_driver, ...);However, the system crashes with a HardFault inside: SCB_InvalidateDCache_by_Addr()which is called from: fx_media_open() ->fx_stm32_mmc_driver() ->mmc_read_data() ->invalidate_cache_by_addr() CopyEdit   

Hello ST Community,I'm working on an STM32H753VIT6 project and need to upgrade FreeRTOS from v10.3.1 to v11.2.0 due to cybersecurity requirements. I've encountered several integration challenges that I'd like to share and seek guidance on.BackgroundCurrent Setup:Working on an STM32H753VIT6 microcontrollerFreeRTOS v10.3.1 with CMSIS-RTOS v2 wrapper automatically generated using CubeMX which works seamlessly out of the boxTarget:Using the newest FreeRTOS v11.2.0 from official repository (preferably without the CMSIS wrapper so future upgrading will be easier): https://github.com/FreeRTOS/FreeRTOS-Kernel/releases/tag/V11.2.0The process:So I followed some guides from the FreeRTOS forums and the ST community forums.Like this one: https://community.st.com/t5/stm32cubemx-mcus/is-there-a-way-to-disable-the-automatic-default-task-creation-when-c-2560/td-p/256903where I've been told there is no other way of upgrading (at least for my STM32H753VIT6) than deactivating the FreeRTOS from within the

Hi All,I am quite new to bootloaders and I wanted to understand best approach to upgrade the firmware. I will get the firmware from a 4g module and store it in external flash. We are based on STM32U5A5 mcu and it will always use the application present in the internal flash. External flash will have two copies/slots. Current one for rollback and new downloaded one.I am thinking about the following approach. I was wondering if there is anything build-in to do this? I suppose almost everybody must be using the same approach.Is there any stm32 bootloader that can do the same? If custom bootloader is needed is there any template I can follow?Thanks,Sandeep  

It seems there's a bug in the HAL library causing data bytes to be mixed with memory address bytes when sending data using HAL_I2C_Mem_Write_IT function. The issue was observed on STM32L162VET6 while using I2C as master at 300kHz speed. It is caused by the condition in HAL_I2C_EV_IRQHandler (stm32l1xx_hal_i2c.c) on line 4808.The issue happens after TXE interrupt occurs (DR is waiting for another byte of data) and your interrupt routine is not fast enough to provide DR with another byte of data, before all bits from SHIFT register are sent out. In that case, a BTF interrupt occurs, causing the code of the HAL_I2C_EV_IRQHandler to go for I2C_MasterTransmit_BTF instead of I2C_MasterTransmit_TXE function. The problem is, that I2C_MasterTransmit_BTF doesn't handle memory address. It only copies another byte of data from data buffer. The issue is invisible when the situation happens while sending out the data buffer. But if it happens during sending out the memory address it causes