STM32 MCUs Embedded software

Hi, I'm have a trouble with UART Interrupt when using FreeRTOS.I want to receive a string buffer send from Serial Terminal ( Hercules Software ) using UART interrupt mode. But when I send data, I just receive 2 character. Ex: When I send "Resume", I just got echo back 2 line: "Rx_data:R","Rx_data:e".Has anyone else encountered this problem? Please share a solution with me.This is my call back function: void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; HAL_UART_Receive_IT(&huart1, &Rx_data, 1); if(Rx_data == '\n') { Rx_buffer[Rx_index] = '\0'; if(strcmp((char*)Rx_buffer,"Resume") == 0) { xTaskResumeFromISR(AboveNormalHandle); } Rx_index = 0; } else { if(Rx_index < sizeof(Rx_buffer)-1) { printf("Rx_data: %c \n",Rx_data); Rx_buffer[Rx_index++] = Rx_data; } } portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } 

Many small format LCD displays do not provide parallel RGB interfaces but instead rely on high-speed serial interfaces such as QSPI. To support this class of display is it possible to use the XSPI peripheral in QSPI mode to drive them? An example LCD controller transaction is shown here:  The data line mapping is as follows:SDI_SDA -> IO0DCX     -> IO1D[0]    -> IO2D[1]    -> IO3

stm32_IEC_project_CM7.elf [cores: 0]Thread #1 [main] 1 [core: 0] (Suspended : Signal : SIGTRAP:Trace/breakpoint trap)0xfffffffe<signal handler called>() at 0xfffffff1HAL_TIM_IRQHandler() at stm32h7xx_hal_tim.c:3,777 0x8055b74TIM3_IRQHandler() at stm32h7xx_it.c:185 0x804a352<signal handler called>() at 0xfffffffdprvPortStartFirstTask() at port.c:267 0x8065f78xPortStartScheduler() at port.c:379 0x806608cpxPortInitialiseStack() at port.c:214 0x8065ed0   This is the error which comes suddenly. here i use tim3 as base source for the tick interrupt of task scheduler as replace of  systick. Previously this code works fine. suddenly creates issues in worked hardware itself  . after some time device works and fails randomly but same code what reason    

Hello, I saw the thread below and now a bit confusedhttps://community.st.com/t5/stm32-mcus-embedded-software/update-about-usb-pd-stack-to-support-epr-mode/td-p/829168It says EPR is supported with a TCPP package but the TCPP-M18 itself - rated to 100W max.  Do I install the software package but do not put TCPP chip? If so How do I know which functions I need to Disable/enable because I know TCPP communicates with MCU over I2C (which is hidden BTW in main.c)

I want to calculate the resistance/power of an AC heating element by measuring voltage (via a voltage divider) and current (using an ACS71240 current sensor). The hardware setup is fine. I get the expected values. I checked this when using Arduino Framework's analogRead(). But that call is so slow (because it does the whole ADC initialization and deinitialization every time), that there's too much time between the voltage and current measurement.So while I'm still using the Arduino Framework for most of the code, I've used CubeMX to configure the ADC with DMA and integrated that code into mine. I initialize the ADC/DMA, run one ADC calibration, then in a loop call HAL_ADC_Start_DMA(), wait on a dma_complete variable, that is set in the HAL_ADC_ConvCpltCallback(). This works ... almost.At some point the values of the channels end up in the wrong order in the DMA buffer. So the second channel's conversion result is first in buffer and the first's in the second place. This

This example work perfectly using non interrupt driven UART HAL library, HAL_UART_Receive and HAL_UART_TransmitAny idea on changing to HAL_UART_Receive_IT and HAL_UART_Transmit_IT?Many thanks https://forum.digikey.com/t/easily-use-scanf-on-stm32/21103

I'm trying to make audio equipment using stm32f446re board and pcm5102 module. When I used the audio equipment, when I sent music using i2s communication, the output came out well, but when I finished DMA setting after selecting i2s protocol in sai, the output didn't come out smoothly. (DMA checked operation using callback)Also, I checked pcm5102 can be operated no external sck.What's the problem?   

Hello,I am working with STM32 IDE v2 and stm32u585 processors. I have a project which is configured with the help of stm32 cube mx and has its own core/Drivers/.ioc files. It is like a ground for using the processor together with other external modules, like sensors, flash chip, LED drivers which are on the same PCB together with the MCU. I have two products using a processor of this family - one is with 64 pins and other with 100 pins. But they have basiccally the same hardware design and use the same pin mapping and peripherals as close as possible to one another. So both can use the same ground project and its configuration and picking different peripherals based on needs. The customer interface is defined separately, in a project that used to be called Application where MMI part is. It is a higher level project and does not need to know what hw there is. Before it was possible to have the ground project as a submodule to  a couple of application projects and it was building wi

I'm checking the output of internal opamp in the STM32U083C-DK.In both PGA and Follower modes, I found that the opamp output voltage was lower than the actual input signal. Follower mode/before calibration(Factory trim/0xe13): - Input signal: 0.2502V -> Output signal: 0.2488V PGA mode(Gain: x8)/before calibration: - Input signal: 0.1010V -> Output signal: 0.7942V So, I used the opamp's internal calibration function. Follower mode/after calibration(User trim/0x1f12): - Input signal: 0.2502V -> Output signal: 0.2350V PGA mode(Gain: x8)/after calibration(User trim/0x1f12): - Input signal: 0.1010V -> Output signal: 0.6852V However, the opamp output signal level was further reduced, indicating that something was wrong.Before calibration, the opamp's factory trim code was 0xe13, but after calibration, the user trim code was set to 0x1f12. It appeared that the P terminal calibration value was set to the max (0x1f). (As an additional condition, I opened SB12 on the STM32U083C-DK bo

Custom board. STM32U5G9. I am running Zephyr and trying to use PB8 and PB9 for the FDCAN peripheral. In loopback mode, it does not get any errors but in normal mode it does. The odd thing is that if I change the pins in the dts file to PA11 and PA12, it works fine.  I am guessing that it is a timing/clock issue or something but I have been arguing with this for two days and I am out of ideas. The device tree entry is: &fdcan1 { // pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>; pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>; pinctrl-names = "default"; bus-speed = <250000>; bus-speed-data = <250000>; status = "okay"; can-transceiver { max-bitrate = <250000>; }; }; If I uncomment the first pinctrl (pb8 & pb9) I see no output on the TX GPIO pin (PB9). If it is configured as shown, I do see packets on PA12.   Thanks!

Does ST maintain any automated tests for ST development boards and Zephyr?  If so, where may I find more details about the hardware used and test coverage?

Not sure that I have the latest version of the HAL but I used two ip address for the ETH MAC and tried to enable both in the L3 filter.But I could not get any data to the second interface. with the filter turned on-Looking more closely on the HAL_ETHEx_SetL3FilterConfig I found what can only be a copy paste mistake.Writing the destination address for IPv4 was mede to the MACL3A0R1R register instead of the expected: MACL3A1R1RMight be fixed in newer version but using two IP-address perhaps is a bit unusual.  

Hello, I have a query about how HAL_UART_Receive_DMA and HAL_UARTEx_ReceiveToIdle_DMA work?For my application there is a varying payload size, so I am wondering how would I trigger the HAL_UART_Receive_DMA(&huart3, rx_buffer, 4096, 0xFFFF); interupt? As from my understanding it would be waiting for all 4096 bytes of data which won't arrive unless a different frame was sent.Whereas  HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, 4096); triggers once the serial port stops communicating, however it stores the received data in 512 byte chunks, which has proven difficult to access when generating a LUT from the rx_buffer.If anyone can shed some insight over how these interrupts work? And how to make them applicable for a variable payload would be great.

I have implemented a USB Audio 2.0 device that receives audio from the PC host (speaker endpoint) and loops it back (microphone endpoint). The PC correctly recognizes the device, and audio playback works, but I'm experiencing unexpected low-frequency noise.Specific symptom: When playing a pure 350Hz sine wave from the PC, the device receives not only the sine wave but also significant noise content from 0Hz to 350Hz. This noise is audible in the loopback audio sent back to the host.The audio data flows through a simple memory copy without any DSP processing:ux_utility_memory_copy(write_buffer, read_buffer, copy_len); ux_device_class_audio_write_frame_commit(g_mic_stream, copy_len);I also perform FFT analysis for visualization (TouchGFX), and the spectrum confirms the low-frequency noise is present in the received audio data itself, not introduced by my processing.I have tried to disable the microphone endpoint and keep just the speaker endpoint but the issue persists.Any guidance on di

what am i doing wrong?

Hello ST Community,I’m working on bringing up audio capture using the X-NUCLEO-CCA02M2 microphone expansion board with the NUCLEO-N657X0-Q (STM32N6), and I’m struggling to obtain any audio data.According to the CCA02M2 documentation, the board is compatible with STM32 Nucleo boards via the ST-Morpho connector and supports acquisition through I²S, SPI, DFSDM, or similar digital audio peripherals. However, I have not been able to find any example, tutorial, or application note specifically targeting STM32N6 devices.My goal is to run an Edge Impulse audio model on the STM32N6.I was able to successfully run inference using manually provided raw features from the example in this repository:https://github.com/edgeimpulse/example-standalone-st-stm32n6So the ML pipeline itself is working correctly.My difficulty is specifically with capturing audio from the X-NUCLEO-CCA02M2, due to lack of clear documentation or examples for STM32N6 boards.My setup:• Boards connected pin-to-pin through ST-Morph

Hello ST Community,I am facing this issue developing firmware on the NUCLEO-N657X0-Q (STM32N657).My architecture involves a standard FSBL that jumps to a main Application.Application:Interfacing with a Adafruit BNO085 IMU via UART (3 Mbps) using the CEVA SH2 driver, adapting the official CEVA SH2 example code of this repository to my Nucleo. The driver uses USART2 with GPDMA1 Channel 0* (Circular Buffer for RX).Setup Details:MCU: STM32N657X0Peripheral: USART2 (3 Mbps) + GPDMA1 Channel 0 (RX Circular Buffer).Timer: TIM2 (used for microsecond timestamping in the driver).Cache: Disabled (to rule out coherency issues).Symptoms:1. FSBL: If I initialize and run the sensor logic inside the FSBL, it works perfectly.2. Application: If I move the exact same logic to the Application (after the jump), the code hangs inside the driver's code.3. Breakpoint fixes the problem: In the Application, if I place a breakpoint at the beginning of the shtp_service() function (called period

Hi everyone,I’m reaching out because I’m having trouble setting up a USB HS CDC (Communication Device Class) using the internal PHY, without VBUS sensing.I use STM32H7S3I8T6.My program gets stuck in the following loop before timing out: /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; do { count++; if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); return HAL_OK; }Despite searching through various forum topics, I can't seem to get it to work.Here is my STM32 configuration:Clock : USB Clock :  Power Regulator :USB HS Configuration :USB_DEVICE Configuration :Here is my configuration.I would be very grateful for any help you can provide.Thanks in advance,Paul

I have flash update operations working fine on an STM32U535 with 512kB flash, but am getting an error on a 256kB device.  Driving into the debugger, I find it coming out of the FLASH_WaitForLastOperation HAL routine, specifically after: reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR) which returns 0b10001000, which winds up being the FLASH_NSSR_PROGERR, and FLASH_NSSR_PGSERR.  I am not sure why.   Code segment enclosed here: const uint32_t NVRAM = 0x0803E000; FLASH_EraseInitTypeDef EraseInitStruct = {0}; HAL_StatusTypeDef hfError; uint32_t PAGEError = 0; // To hold any page error code uint32_t pageNumber = (NVRAM - 0x08000000) / 0x2000; uint32_t progAddress = NVRAM; uint64_t *pSource = (uint64_t)&memory[0x1800]; // 1800 uint32_t quadWordCount = 0xFF / 16; if (HAL_FLASH_Unlock() != HAL_OK) { printf("Cannot erase FLASH memory.\n\r"); // Handle error, e.g., print error message return; } // Clear

hi, i trying DTLS on netXduomy goal is TLS and DLTS running independently (STM32H5 is server, PC is client) so i success mutual TLS(Ver 1.3) but failed DTLS runningi'm in situation that DTLS connection is completed at client but server is not answer about client hello(3 time ignored) i check variables and found handler pointer is null - active_dtls_session->nx_secure_dtls_tls_session.nx_secure_session_cipher_handler_server == nullso i guess DTLS initialization was not completed but i don't know what do i do i attach my code and variables please help me thank you DTLS_SESSION_CONFIG g_dtls_session_table[1]; #pragma data_alignment=8 NX_SECURE_DTLS_SERVER dtls_server; typedef struct { NX_SECURE_DTLS_SESSION sessions[1]; ULONG padding; UCHAR metadata[32*1024]; } DTLS_MEMORY_BLOCK; NX_SECURE_DTLS_SESSION *active_dtls_session = NULL; UCHAR dtls_reassembly_buffer[32*1024]; UCHAR dtls_client_cert_buffer[20*1024]; #pragma data_alignment=8 DTLS_MEMORY_B

Hello, I am using the HAL for multi-master SMBUS operations on an STM32H753. I ran into a scenario in which the event handler interrupt function (I2C4_EV_IRQHandler() in my case) was repeatedly firing such that there was no CPU available for other code to run. It seems that the logic within HAL_SMBUS_EV_IRQHandler(), which the above function calls, may not be correctly identifying the source of the interrupt, and not clearing it. This code: /* SMBUS in mode Transmitter ---------------------------------------------------*/ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { calls SMBUS_CHECK_I

Hello. How to configure the FreeRTOS LwIP bundle correctly on the STM32F407VET6 and PHY Lan8720, I'm configuring it in the Cube IDE. There is a ping without FreeRTOS, but there is no ping with FreeRTOS. Thank you very much.

hi all! i'm handling Foc-pmsm project, i use communicate ETH with other board via ETH but it connect too slow and open lost connection, i don't what issue because this is the first time i handle with ETH. can you help me take a look and show my mistake

Background: I am using the STM32H747I-DISCO board and the BSP SDMMC example from the ST Repository as my starting point.  I can provide my code if necessary but wanted to keep post as short as possible.  I have looked at AN4838, AN4839 and AN5200 ST Micro Documents.  They are detailed but not getting me to my answer fast enough.   My Goal:I am trying to understand the detailed reason(s) why I need to enable the D-Cache when using FatFS calls with the SDMMC peripheral on the STM32H747I-DISCO board to avoid a timeout and also why I-Cache does not necessarily need to be enabled.     My Understanding to this point: The CLIFF NOTES of what I think I understand (between the ST documentation, AI hallucinations and true answers): Enabling the D-Cache reduces AXI bus contention since the IDMA in the SDMMC peripheral needs AXI bus to move data from the FIFO to SRAM on a very tight timeline, mandated by the SDMMC peripheral.  When you enable the D-Cach

Hi all,I'm struggling to get SPI working on my STM32U5G9J. I have an nordic master device outputting 6 bytes of data every 500 ms over SPI and plugged into the proper pins, double checked and confirmed on analyzer.stm32u5g9j_dk2.overlay/ { aliases { spi-slave = &spi1; }; }; &spi1 { status = "okay"; pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5 &spi1_nss_pb0>; pinctrl-names = "default"; /delete-property/ cs-gpios; fifo-enable; };main.c#include <zephyr/kernel.h> #include <zephyr/logging/log.h> #include <zephyr/drivers/spi.h> #include <zephyr/drivers/gpio.h> #include <zephyr/sys/util.h> LOG_MODULE_REGISTER(main); #define SPIOP (SPI_OP_MODE_SLAVE | SPI_WORD_SET(8) | SPI_LINES_SINGLE | SPI_TRANSFER_MSB) static const struct device *spi_in_dev = DEVICE_DT_GET(DT_ALIAS(spi_slave)); static const struct spi_config spi_in_cfg = { .frequency = MHZ(1), .operation = SPIOP, .slave = 0, }; int main(void) { if (!dev