STM32 MCUs

I just discover that the TouchGFX tool run only on Windows ...:(I do not use Windows and I have no plan to use it one day.Do you know if it run on Linux with Wine ?Thanks

The G491KCU6 part has 256 KB flash. The G4A1KEU6 has 512 KB. Ref man (Table 1) hasNo mention of 256 KB G491 part. Is it category 4?

If, like me, you are attempting to use this device and believe there are gaps in the information available, you are correct. However, the information you seek, plus additional advice and assistance is available from ST, you simply have to ask via a ticket on ST.COM. I will update this post when I have completed my project.

Has anyone else experienced a power supply brown-out/crash when running the NUCLEO-H755 (or any other NUCLEO) at the maximum clock speed with quite a few peripherals enabled?  I am suspicious that the 5V/0.5A power provided by USB is not enough to power everything at full speed when using both cores, 100Mb ethernet, and various counters and serial interfaces.  Reducing the clock to 400 MHz seems to resolve the issue.From looking at the board schematics, it appears that using the 5V EXT power supply input will feed the main 3.3V LDO regulator directly which supports 1300mA of current.  However, I don't think this LDO can handle the additional thermal power loss (1.7V x 1300mA =~2.2 Watts of heat) without adding a large heat sink...

Hello,I am building and application with a STM32U575 and a 4Gb NAND Flash. What I am trying to achieve now is to upload files from my PC through USB and then used these file within the STM32 using FileX.I already managed to set up FileX and LevelX to create and manipulate files within the MCU. Then I managed to get a USBX MSC device to appead in windows, with correct capacity, name etc..Finally I tried to implement the read/write functions in ux_device_msc.c by using the FileX function fx_media_read and fx_media_write. And not I have some issues in the wrinting method.If I implement the read function "USBD_STORAGE_Read" only, leaving the write function empty, everyting works fine. I am able to find and read my files from windows.From the moment I implement the USBD_STORAGE_Write function, nothing works anymore. In this configuration, the USB MSC apprears in windows with a capacity of 0 octets and windows stalls if I try to access it. After some digging, I found out that windows tr

Hi,I was testing the End Node example on a custom board equipped with a STM32WL5MOC module. However, I changed only the UART from UART2 to UART1 in platform settings. I also activate the DMA. However, I can get only "APPLICATION_VERSION: V1.3.1" on the UART terminal and no other messages. Someone knows why?Thanks.Matteo

Hello ST Community,I’m working on a custom board based on STM32WB55 and need to implement secure OTA firmware updates (signed and encrypted images).Here’s what I’ve done so far:I successfully tested SBSFU in local loader mode (YMODEM over UART).→ Pushing a *.sfb image works perfectly (signature + AES encryption validated at boot).Next, I tried integrating SBSFU + BLE_OTA (both on a Nucleo board and on my custom board).→ BLE OTA works for transferring a raw .bin, but that binary is neither signed nor encrypted, which defeats the purpose of SBSFU security.→ I expected to be able to push a *.sfb file from the ST BLE Sensor app, but that’s not supported.My question:What is the correct way to perform a secure OTA update (with signed and encrypted image) on STM32WB55?Is there an official workflow or example for using BLE OTA as a transport for SBSFU .sfb images (instead of raw .bin)?Any guidance or references (sample projects) would be greatly appreciated.Thanks in advance!— Guilhem

Our team is using the STM32G0 with the USBPD stack and the TCPP02-M18 as the protection circuit. Please find the attached schematic for reference.We are configuring the PD contract with a maximum of 15V, 3A. When connecting an HP G11 laptop to the USB-C port, the contract is successfully negotiated, but we observe repeated hard resets. Upon investigation, the resets are linked to the TCPP nFAULT signal going low, indicating an overcurrent fault.When we short the sense resistor (R10) in the schematic, the fault does not occur. We also tried adding a 0.1 µF capacitor across the sense resistor, but the fault still occurs.When we limit the PD contract in software to 15V, 2.9A, the faults no longer appear. We are using Nexperia GANB4R8-040CBAZ MOSFETs, which have a drain-to-gate capacitance greater than 20 pF, so an additional capacitor should not be necessary.We also tried reducing the sense resistor R10 to 7m Ohms, but the same overcurrent fault still occurs. Please see the attached scope

Hi ,I'm working on the STM32H7S7L8-DK and i would like to know if it is possible to use both USB_FS and USB_HS as two separate Virtual-port-com Device mode When I try to do it for one it is impossible in cube MX to do it for the other.Thanks !  

Hello ST Community,I am designing a residential pump driver product that requires a Variable Frequency Drive (VFD) to control a three-phase AC induction motor. I am using the STM32 Motor Control SDK as a reference, specifically the AC induction motor page.https://wiki.stmicroelectronics.cn/stm32mcu/wiki/STM32MotorControl:SDK_AC_induction_motorMy goal is to find the most cost-effective STM32 MCU that can reliably implement this control. Is there a cheaper alternative to STM32G431RB? For example, can i use STM32F0 or G0 series?Also is there any other reliable solutions except for MCSDK which may lead to this goal, meaning a lower BOM cost?Is there any plan to add ACIM driver support in MCSDK V6.X in future?Thank you for your time and expertise.

Hi, My current project using 2 STM32WB5x series MCU and after added in Zigbee feature through STM32CubeMX, it is always loops at the Idle code as shown below. The code is from the stm32_seq.c ----------------------------------------------------------------------------------/* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING;/* if a waited event is present, ignore the IDLE sequence */if ((local_evtset & EvtWaited)== 0U){UTIL_SEQ_PreIdle( ); UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( );local_taskset = TaskSet;local_evtset = EvtSet;local_taskmask = TaskMask;if ((local_taskset & local_taskmask & SuperMask) == 0U){if ((local_evtset & EvtWaited)== 0U){UTIL_SEQ_Idle( );}}UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( ); UTIL_SEQ_PostIdle( );}---------------------------------------------------------------------------------- From the debug traces output by the USB VCP below s

IAR/EWARM can connect to my STM32WL55 nucleo board.  However, I get a complaint about a hardware fault during loading.  It also claimed that the STLINK firmware was old, so I decided to update that.STM32CubeProgrammer would not initially start, so following directions based on the theory that the JRT was messed up, I reinstalled.So, cube programmer now starts, but it says not connected.  There is a downward pointing arrow that I can press on without any obvious effect other than a focus box. Has anyone experienced something similar -- and of course how did you fix it? 

Hi,I have a custom board with a STM32WB5MMG module. In order to obtain the best performances, I want to use the STM32WB5MMG SMPS with a 3.3v voltage source. However, I can't find in the Cube IDE any command to activate the SMPS. Is it always activate? How can be used and activated? Thanks

What is the meaning of the FLASH_OBKCR.NEXTKL field while executing within HDPL_0 (e.g., during execution of ST RSS)?This question might seem irrelevant to me as I'm a user and user code will never execute within HDPL_0, but it might be important from a threat modeling point of view: does ST (by means of its RSS code) have access to HDPL_x user-provisioned AHKs (Application Hardware Keys) where x >= 1?The reference manual states the following:5.9.18 FLASH option byte key control register (FLASH_OBKCR)"NEXTKL[1:0]: Next key level00: OBKINDEX represents the index of the option byte key stored for the hide protection levelindicated in SBS_HDPLSR.01: OBKINDEX represents the index of the option byte key stored for the hide protection levelindicated in SBS_HDPLSR plus one (e.g. if HDPL=1 in SBS_HDPLR the key of level 2 isselected).10 or 11: reserved"Does this mean ST RSS (HDPL_0) can access:HDPL_0 AHKs (when NEXTKL=00)HDPL_1 AHKs (when NEXTKL=01)but not:HDPL_2 AHKs (no applicable NEXTKL v

Hi everyone,I have a question regarding the compatibility between I3C and I2C devices on the STM32H533RETx.I’m using the I3C2 interface on my MCU:PC6: I3C2_SCLPC7: I3C2_SDAOn this bus, I have only one device connected – an I2C EEPROM (M24C32-RMN6TP).The MCU acts as the master, and the EEPROM is the only slave on the line.My question is:Can I read and write to this I2C EEPROM using the I3C2 port in I2C-compatible mode, just like with a normal I2C interface?Or are there any known issues or limitations when using the I3C peripheral to communicate with standard I2C devices (in my case, only one slave device on the bus)?Thanks in advance for your help and insights!

[PN]: STM32G473CBUX[VERSION]: 6.4.1[TOOL]: Motor Control Workbench[DETAILS]:In this design, which I tried to setup exactly as my previous working projects, the ASPEP comms code seem to have setup interrupts to occur on UART Rx and not Tx and Rx DMA is not setting flags to allow comms in check in systick handler, line 227 in "stm32_mc_common_it.c".[EXPECTED BEHAVIOR]: On other projects setup (with eg STM32G431VBTX) in similar fashion, Tx interrupts occur in UART IRQ handler, DMA_TC flag is set for UART Rx.[HOW TO REPRODUCE]: Compile from MCW6.4.1 to Stm32CubeMx to STMCubeIDE and run on custom hardware, but maybe you can check some other way why Tx and Rx DMA and interrupts have gotten swapped in this code compared to previous projects.

Title edited to name the device being hosted. Hello , I am currently trying to configure STM32F407 board as USB host. The code for it is given below. I am not receiving anything from the USB device(bus powered). I have a doubt that it might be related to the hardware of it(VBUS). The rest of the code is generated by the IDE itself so there is no doubt related to it. I have configured it as USB host only mode. I am new to embedded systems so any kind of help would be appreciated. Is there anything wrong with the code or any links to help me configure the USB host.I would be glad to clarify any queries related to the above.

I am using Nucleo STM32H753ZI board. The STMCube IDE version is 1.19.0 and FreeRTOS version is 1.3.1 and CMSIS RTOS1 version is 1.02 I have enabled Icache, DCache and MPU. Integrated the stacks of LWIP,Ethernet and FreeRTOS too.Basic ping functionality is not working.Could you please look into this.

Hi,is there any way to use the pads pc8 and oc9 on the morpho header of tve nucleo h753zi? They are lebeled but dont receive signal. I see the signals on the according pins of the zio header.right now I am thinking of drilling the morpho pads away and connecting through the hole patched from the zio header. I was hoping for a better way thanks for helping

I am using the HAL FDCAN driver in queue mode (STM32G431, FW_G4 V1.6.1).The application is (intentionally) working with a high bus load (~90%), so it is expected that there will occasionally be times when there are no transmit message buffers available - so HAL_FDCAN_AddMessageToTxFifoQ() is expected to return HAL_Error, as that is what it does if this is the case.The application code can then use HAL_FDCAN_GetError() to get the ErrorCode (though this seems a bit pointless, as instance->ErrorCode does the same, so not a lot of abstraction here).However, it only becomes clear from looking at the HAL code that ErrorCode uses bits to represent the set of possible errors - so it is not as simple as comparing the value with HAL_FDCAN_ERROR_FIFO_FULL (the test needs to use a mask operation). The documentation does not explain that this is the case.How should the error be cleared once it has been handled? The HAL does not provide an API for this, so it appears as if the user

We design a new product where we use STM32WL microcontroller and in the datasheet ST is recommended to use NT2016SF-32M-END5875A manufactured by NDK but we dont found it to buy.Can you provide some distributors where we can buy this TCXO?Can you provide other alternative TCXO to NT2016SF-32M-END5875A?Thanks a lot and best regards

Hi,I'm working on a project using STM32H733 and Azure RTOS. I have written my own implementation of malloc and other memory allocation functions. I'm using the `tx_byte_pool_create` function to first create a byte pool in SDRAM and then using `tx_byte_allocate` in my custom malloc to allocate memory from the byte pool.The byte pool is created successfully in SDRAM, and I can also see the contents of SDRAM. Everything seems to work fine.I'm able to ping my device, etc. However, as soon as I trigger an API to hit an endpoint running on an HTTPS server, the device triggers the callback function. While preparing the response, it encounters one of the memcpy operations (where the HTTP server allocates memory and stores the buffer in SDRAM) and gets stuck in the Hard Fault Handler.Work-Around: I replaced `json_asprintf` with `sprintf` and passed it with a memory block allocated in SDRAM using a custom malloc implementation. And it worked, I successfully got a response from the HTTPS server.

Hi all,i see H7 supports clause 45 MDIO access, but in the HAL library looks not implemented, i see only clause 22.How should i proceed to read/write c45 ? Thanks,angelo

Hi ST team,I'm using STM32H743IIT6 with REV_ID=0x2003 and encountered a problem. Quadspi dual-flash indirect read mode is used for continuous reading data from external. According to RM0433, If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4-Gbyte flash memory), then in this special case, transfers continue indefinitely. But I found that after the 1st 4GB is transferred, the frequency of QUADSPI CLK pin dropped to it half value, for example from 2MHz to 1MHz, without any error indicator. After that, the 2nd, 3rd and so on, 4GB transfer will remain 1MHz clock operation continuously. Meanwhile, the duty cycle of CLK is changed to 25%, as follows:     I read configuration registers of PRESCALER in QUADSPI_CR and other clock configuration registers after clock frequency dropped, they are not be changed. And the patch of 2.7.4 "QUADSPI internal timing criticality" in ERRATA_DATASHEET has been added. Our congfiguration of QUADSPI is lis

I use stm32h7r3 to develop USB audio recording function. My device can work successful in Ubuntu/Android/Windows, but failed in iOS. I had tried many iOS version, but still can't work.  The below is my device USB parameters:2 channels L/R32 bit  data length48KHz sample rateHigh speedUAC1.0my reference code(stm32F769I) from https://www.st.com/en/embedded-software/x-cube-audio.htmlCould someone give me some advice?