STM32 MCUs

On an STM32U5G7VJTX I'm using a custom board with an ILI9488 480x320 display in 16-bit mode on the FMC.I am using NemaGFX version 3.5.0 for the STM32U5x9 as I don't have STM32U5x7.Drawing lines for a test works fine as long as I skip the nema_cl_wait() function, which hangs forever.To give GPU2D time to finish the work, I replaced nema_cl_wait() with a short loop that takes enough time. But that's obviously not a good idea, as some tasks can take longer or shorter.On the STM32U5G9J-DK2 Discovery kit the same GPU2D stuff runs just fine!Is this because the GPU2D in the STM32U5G7VJTX isn't exactly the same as in the STM32U5G9ZJT6Q?I've experimented with the GPU initialization in nema_hal.c, but without solving this issue.Does anyone have any ideas?/** * @brief Draws a line * [in] x1 * [in] y1 * [in] x2 * [in] y2 * @return None */ void Draw_Line(float x1, float y1, float x2, float y2) { /* Create GPU Command List */ Display.NemaGFX.cl = nema_cl_create_sized(8192);

Hello STM32 enthusiasts,While testing NemaGFX v1.3.0 for the STM32H7RS (M7), I discovered some differences compared to NemaGFX v3.5.0 for the STM32U5x9 (M33).1. nema_clear(color); Doesn't work, I had to come up with some solution: nema_matrix3x3_t m; NEMA_VG_PAINT_HANDLE paint; uint32_t color = nema_rgba(0xFF, 0xFF, 0x00, 0xFF); /* Fill the screen with a color */ #if defined(STM32H7S7xx) /* Use this on STM32H7RS */ paint = nema_vg_paint_create(); nema_vg_paint_clear(paint); nema_mat3x3_load_identity(m); nema_vg_set_fill_rule(NEMA_VG_FILL_NON_ZERO); nema_vg_paint_set_paint_color(paint, color); nema_vg_draw_rect(0, 0, DISPLAY_SIZE_W, DISPLAY_SIZE_H, m, paint); nema_vg_paint_destroy(paint); #else /* Does not work on STM32H7RS */ nema_clear(color); #endif2. nema_bind_src_tex / nema_blit Does not work with the NEMA_AL88 format, but luckily it does work with the NEMA_ARGB8888 format.// Format = NEMA_AL88 /* Doesn't render any output using AL88 bitmaps */ Format = NEMA_ARGB88

 Hello everyone,I am working with STM32G431CBT6 using Keil MDK. I want to develop a bare-metal project (without CubeMX or HAL).However, when I open Manage Run-Time Environment (RTE) in Keil, under the Device section I only see the CubeMX option. The “Startup” component is not available.What I expect:Under:Device → StartupI expect to see the standard startup files for STM32G4 series so I can build a bare-metal project using only:CMSIS → CORE Device → StartupWhat is happening:Only CubeMX appears under the Device section.The Startup option does not show up.Additional Information:MCU: STM32G431CBT6Toolchain: Keil MDKProject type: Bare-metal (no HAL, no CubeMX)I have selected the correct device in "Options for Target → Device".Could this be related to the STM32G4 Device Family Pack (DFP) installation or version?Is there any specific pack configuration required to enable the Startup component?Any guidance would be appreciated.Thank you. 

Hello. I purchased two STM32F407VGT6 controllers from different sellers. Later, I noticed that the markings were different. Is it possible to determine the originality of the chip based on the markings? The absence of the ARM label is alarming, and the VGT6 parameters have the number 6 on a separate line.

We are using STM32G030C8T6 (LQFP48 package) in a new design and need clarification regarding pin 36: PA14‑BOOT0, which according to the datasheet serves both:SWCLK (Serial Wire Debug clock)BOOT0 (boot mode selection)In our earlier designs using similar STM32 devices, BOOT0 and SWCLK were separate pins. BOOT0 was typically pulled down, and SWCLK required no external pull.However, in the STM32G030 series, BOOT0 is multiplexed on PA14, which is also SWCLK. The datasheet states that upon reset, PA14 is configured as SWCLK with an internal pull‑down enabled.We would like clarity on the following points:Is an external pull‑down resistor required on PA14‑BOOT0, or is the internal pull‑down on PA14 sufficient for all conditions?Will adding an external pull‑down interfere with SWCLK operation during debugging?Are there recommended application notes or hardware guidelines specific to STM32G0‑series devices where BOOT0 is multiplexed with SWCLK?

Hello everyone, I'm having some trouble implementing I3C communication and would like to ask for some help. I am using the NUCLEO-H503RB board as my main controller. For the target devices, I have the NUCLEO-IKS01A3 expansion board and the TSC1641 (Click Board) connected. I'm currently facing some issues with the I3C communication setup between these components. I have successfully managed to read the WHO_AM_I ID from the LSM6DSO (on the NUCLEO-IKS01A3). However, when I attempt to read the ID from the TSC1641, the SCL line continues to output a clock signal (or stays toggling) without a proper response. I am seeking assistance in analyzing the root cause of this issue. 

Split from STM32G0B0: RM0454 link out-of-date ? - this is a new topic raising issues in the document itself.Hi @Amel NASRI ,Thank you for your quick answer.I have however encountered a few errors in that RM0454 Rev 5 that are different/fixed in RM0444 Rev 6. For example, the following is all done on an STM32G0B0CE (512kiB) rev Z.Erasing a flash page (page 78/989) PNB's limit should be 128 so it stays limited to the 256KiB of the selected bank using BKER. A higher value (for example 256+) errors the flash controller.If this is correct, the following image should also be incorrect (Table 9, pg 55/989)and be changed toAnother issue that I encountered is that the 512kiB STM32G0B0CE sometimes bricks when attempting to change the option byte DUAL_BANK (pg 81/989)I believe this should also be as in RM0444, 512kiB devices always operate in DUAL_BANK mode. Have I looked over something that caused me these issues? Or could you confirm that these are indeed errors in RM04

I'm trying to make audio equipment using stm32f446re board and pcm5102 module. When I used the audio equipment, when I sent music using i2s communication, the output came out well, but when I finished DMA setting after selecting i2s protocol in sai, the output didn't come out smoothly. (DMA checked operation using callback)Also, I checked pcm5102 can be operated no external sck.What's the problem?   

Hello,I am working with STM32 IDE v2 and stm32u585 processors. I have a project which is configured with the help of stm32 cube mx and has its own core/Drivers/.ioc files. It is like a ground for using the processor together with other external modules, like sensors, flash chip, LED drivers which are on the same PCB together with the MCU. I have two products using a processor of this family - one is with 64 pins and other with 100 pins. But they have basiccally the same hardware design and use the same pin mapping and peripherals as close as possible to one another. So both can use the same ground project and its configuration and picking different peripherals based on needs. The customer interface is defined separately, in a project that used to be called Application where MMI part is. It is a higher level project and does not need to know what hw there is. Before it was possible to have the ground project as a submodule to  a couple of application projects and it was building wi

Hello, I have a nucleo board with STM32H563. I am trying to make a simple application that will take two ADC measurements with regular conversions. I've been going through the refference manual(RM0481 Rev4) and in the ADC overrun chapter on page 1072, It is stated that there is a three stage ADC_DR FIFO, but not much more about it is explained.  My question is: If i create a sequence of 2 channels and trigger them, would I be able to read the DR register twice with value of channel 1 and 2(with an assumption I am using channels 1 and 2), or will the value of channel 1 be overrun by channel 2 value immediately.I don't want to read the data in an ISR after one conversion is completed, I would liek to read them both together after they are both completed.And I don't need a workaround, I am trying to get to know what this ADC can really do. Thanks, Ivan

Hi I have been looking into the boot process for stm32n6 and was unclear about a few things. For booting from external flash the steps are as follows 1. build your app's bin file. The app should be built with the vector table at the start and the linker script should have a base address 0x341804002. Add the header using the signing tool3. Upload the code to flash using extloaderThis is correct right? The second step is what confuses me. I use the command STM32_SigningTool_CLI -bin Project.bin -nk -of 0x80000000 -t fsbl -o Project-trusted.bin -hv 2.3 -dump Project-trusted.binas indicated in https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/NUCLEO-N657X0-Q/Templates/Template. I did a hexdump on the generated Project-trusted.bin file and I have the following questions regarding it 1. The base header and padding header have a combined length of 576 bytes (0x240). After that the app starts. This doesn't line up with the linker script or UM323

Hello all,Currently I have been working on a project which involves reading values using ADC. This is the following connection: AD8495 is used as an ambient temperature sensor. The connections given in the image are taken from the datasheet for adr8495. I have connected the output to channel A0 of my ADC on board with STM32F407ZGT6. The configuration of ADC is as follows. static void MX_ADC1_Init(void) { ADC_ChannelConfTypeDef sConfig = {0}; hadc1.Instance = ADC1; hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; hadc1.Init.Resolution = ADC_RESOLUTION_12B; hadc1.Init.ScanConvMode = ENABLE; hadc1.Init.ContinuousConvMode = DISABLE; hadc1.Init.DiscontinuousConvMode = ENABLE; hadc1.Init.NbrOfDiscConversion = 3; hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.NbrOfConversion = 3; hadc1.Init.DMAContinuousRequests = DISABLE; hadc1.Init.EOCSelec

Hi everyone, I am facing an issue with CAN communication on STM32F446ZCT6, where the CAN controller frequently enters the Bus-Off state. Hardware Details MCU: STM32F446ZCT6 CAN Transceiver: (TJA1042T) I am working with CAN communication on STM32F446ZCT6, and the CAN controller is frequently going into the Bus-Off state. I am using the HSI clock, configured from 8 MHz to 42 MHz, with the CAN clock derived from APB1 = 42 MHz I have enabled Auto Bus-Off Management and tested multiple bitrates (500 kbps, 250 kbps, and 125 kbps), but the issue still occurs. I see bit errors and acknowledgment errors, which eventually cause Bus-Off.Can you please help me to solve this issue.

I am working on STM32h747 series. I am debugging both CM4 and CM7. After a while, CM4 stops responding and the debug messages shows:"Error in final launch sequence: Failed to start GDB serverFailed to start GDB serverError in initializing ST-LINK device.Reason: (4) No device found on target." If I run CM7 independently, it works but CM4 is not responding. I tried to erase the entire board but CM4 is still not responding and the same message is appearing.

 Does anyone have a component to display audio spectral graphs, specifically for the STM32N6570 Discovery?

During Startup,after MX_NVIC_Init();when it jumps into /* USER CODE BEGIN 2 */The code is interrupted by TIMx_UP_M1_IRQHandler() in its routine, (void)R3_2_TIMx_UP_IRQHandler(&PWM_Handle_M1);the code gets stuck at /* We can not change OPAMP source if ADC acquisition is ongoing (Dual motor with internal opamp use case) */ while (0x0u != pHandle->pParams_str->ADCDataReg1[pHandle->_Super.Sector]->JSQR) { /* Nothing to do */ }I'm not able to understand why this is happening. I have not initialized any custom ADC (RCM) yet.Everything that has run, until that point is generated code only.With some research I have understood that the TIM1 update routine is infinitely waiting for the ADC(Injected Conversion) to finish. Is this some kind of race condition ?This doesn't happen always on every boot/startup. Only randomly, some times. If it does not crash at this point, I have not observed it to crash at a later point of time.Am I suppose

I'm checking the output of internal opamp in the STM32U083C-DK.In both PGA and Follower modes, I found that the opamp output voltage was lower than the actual input signal. Follower mode/before calibration(Factory trim/0xe13): - Input signal: 0.2502V -> Output signal: 0.2488V PGA mode(Gain: x8)/before calibration: - Input signal: 0.1010V -> Output signal: 0.7942V So, I used the opamp's internal calibration function. Follower mode/after calibration(User trim/0x1f12): - Input signal: 0.2502V -> Output signal: 0.2350V PGA mode(Gain: x8)/after calibration(User trim/0x1f12): - Input signal: 0.1010V -> Output signal: 0.6852V However, the opamp output signal level was further reduced, indicating that something was wrong.Before calibration, the opamp's factory trim code was 0xe13, but after calibration, the user trim code was set to 0x1f12. It appeared that the P terminal calibration value was set to the max (0x1f). (As an additional condition, I opened SB12 on the STM32U083C-DK bo

Hello, I have an STLINK-V3MINIE that I've connected to a B-WB1M-WPAN1 board with a 10 lead cable. I'm trying to flash firmware/my code onto the board, but am running into some errors.First, I tried uploading my code using STM32CubeIDE, but am hitting a "No ST-LINK detected! Please connect ST-LINK and restart the debug session". Sometimes there is also a GDB server error. Then, I tried connecting and flashing firmware using STM32CubeProgrammer. When I first refresh, the ST LINK is detected and I tried updating it through the "Firmware upgrade" button. In the STLinkUpgrade tool (v3.16.8), I get an "Upgrade canceled, corrupted firmware data", then "Upgrade successful" (sometimes I see "Failure exiting upgrade mode (Error 33)" instead of success). When I refresh the device list and open in update mode again, the version of the ST LINK hadn't successfully updated or changed. When I try connecting through CubeProgrammer, the connection fails and I see "UR connection mode is de

Hi everyone,I'm trying to interface a DVP camera (like OV5640) with the STM32F469I-DISC0 board using the DCMI peripheral in 8-bit parallel mode.What I have:- The camera is configured and outputs data correctly via I2C.- I'm using bare-metal code (no HAL or CubeMX), and SDRAM + USART debug are working.- DCMI pins are being mapped as per the STM32F469 reference manual.- I verified that I can access and remap the following DCMI pins:- D0 – available- D1 – available- D2 – available- D3 – available- D4 – not available(e.g., PE5)- D5 – available - D6 – available- D7 – available- HSYNC, VSYNC, PCLK – availableProblem:- DCMI_D4 is not brought out on any connector** on the DISC0 board. It's internally routed to LCD or unused.- I checked the board schematic and there’s no easy way to solder to it either.My questions:1. Can DCMI work with 7-bit data (skipping D4)? Will DCMI capture still be valid if D4 always reads 0?2. Is there any known workaround for the missing D4 line (e.g., using

Embedded ST-Link via CN1 USB is working fine. I followed the direction as below when external ST-Link v2 was tried on STM32L552ZET6Q Nucleo-144. The error message "No Target" was displayed on STM32CubeIDE with external ST-Link. Could you provide me with any advice?    

Hello everyone,I am working on a custom board based on the STM32U575RGT6 (1MB Flash). I am encountering a hard fault (SecureFault) during the initialization of the Non-Secure application after integrating the SBSFU.Context:Hardware: Custom board with STM32U575RGT6.Initial Project: A working application using TrustZone active + FreeRTOS (generated via CubeMX). The Option Bytes were set to a default 50/50 split (Secure/Non-Secure).Goal: Implement a Secure Boot / Firmware Update mechanism.What I did:I used the ST example for B-U585I-IOT02A as a reference.I integrated SBSFU_Boot and SBSFU_Loader into my project folder.I adapted the linker scripts (.ld), postbuild.sh, and flash_layout.h to match the 1MB Flash size of the U575RGT6 (vs 2MB on the B-U585I).In my original application, I replaced the .ld files and startup_xx.s files with those provided in the SBSFU_Appli example.Configur

Custom board. STM32U5G9. I am running Zephyr and trying to use PB8 and PB9 for the FDCAN peripheral. In loopback mode, it does not get any errors but in normal mode it does. The odd thing is that if I change the pins in the dts file to PA11 and PA12, it works fine.  I am guessing that it is a timing/clock issue or something but I have been arguing with this for two days and I am out of ideas. The device tree entry is: &fdcan1 { // pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>; pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>; pinctrl-names = "default"; bus-speed = <250000>; bus-speed-data = <250000>; status = "okay"; can-transceiver { max-bitrate = <250000>; }; }; If I uncomment the first pinctrl (pb8 & pb9) I see no output on the TX GPIO pin (PB9). If it is configured as shown, I do see packets on PA12.   Thanks!

Does ST maintain any automated tests for ST development boards and Zephyr?  If so, where may I find more details about the hardware used and test coverage?

This release introduces the latest version of RTEdbg, a high-performance toolkit engineered for real-time embedded system analysis and debugging. The latest update streamlines event visualization via VCD viewers and introduces FreeRTOS trace integration, alongside several core enhancements.Unlike traditional logging and tracing solutions (such as Tracealyzer or SystemView), RTEdbg provides deep runtime insights with a minimal footprint. Its logging functions are significantly faster than commercial alternatives and consume substantially less stack space, making it the ideal choice for both resource-constrained devices and complex, large-scale RTOS-based systems.Relying solely on classical debuggers often feels like "flying blind" when managing intricate timing and RTOS scheduling. RTEdbg bridges this gap by providing:VCD-based visualization for synchronized event and data tracking.RTOS trace support for better scheduling visibility.Enhanced trace macros allowing you to log any data typ

I have been looking at the CRA Q&A and was wondering what you you are meaning with the reporting of security incidents 2026-12-11. Do you mean the reporting according to article 14 that enters into force 2026-09-11?