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Hi,I'm thinking what is the right way to clear HRTIM interrupt status register (HRTIM_ISR) bits?In the description of the HRTIM_ISR register STM32G4 reference manual (RM0440 Rev 8 page 1041) says: This bit is set by hardware when fault 1 event occurs. It is cleared by software writing it at 1.This gives the impression that you can clear HRTIM_ISR bits by writing to this register (HRTIM_ISR)Then again bits of this register are read only ('r')?Then we also have HRTIM interrupt clear register (HRTIM_ICR) (RM0440 Rev 8 page 1042) where we have separate bits to clear HRTIM_ISR bits.So, which is the right way to clear HRTIM_ISR bits? Or can you clear these bits both ways?

Hello,I'm trying to generate a custom PWM output signal with the F103V8TxLQFP100. I took inspiration from here: Custom Signal generation using PWM and DMA - STMicroelectronics CommunityThe basic code looks like this:...uint8_t tempBuffer[10];tempBuffer[0] = 80;tempBuffer[1] = 70;tempBuffer[2] = 60;tempBuffer[3] = 50;tempBuffer[4] = 40;tempBuffer[5] = 30;tempBuffer[6] = 40;tempBuffer[7] = 50;tempBuffer[8] = 60;tempBuffer[9] = 0;(void)htim1.Instance->DIER;while (1){HAL_Delay(500);__HAL_TIM_SET_COUNTER(&htim1, 0);HAL_TIM_PWM_Start_DMA(&htim1,TIM_CHANNEL_1,(uint32_t*)tempBuffer,10);/* USER CODE END WHILE *//* USER CODE BEGIN 3 */}...htim1.instance->ARR = 89;I modified HAL_TIM_PWM_Start_DMA() to enable the TIM update DMA request:__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);I did this because with the trigger on capture compare I got multiple capture compare events in one timer period, when the compare values are assending (30, 40, 50,60).My problem now is: It does

Hello.I am trying to get a custom stm32mp135f to boot.I get following boot messages:NOTICE: CPU: STM32MP135F Rev.YNOTICE: Model: VETON control board based on STM32MP135F - r2WARNING: VDD unknownINFO: Reset reason (0x35):INFO: Power-on Reset (rst_por)INFO: FCONF: Reading TB_FW firmware configuration file from: 0x2ffe0000INFO: FCONF: Reading firmware configuration information for: stm32mp_ioINFO: FCONF: Reading firmware configuration information for: stm32mp_fuseINFO: Using SDMMCINFO: Instance 1INFO: Boot used partition fsbl1NOTICE: BL2: v2.8-stm32mp1-r2.0(debug):()NOTICE: BL2: Built : 12:48:35, Nov 25 2024INFO: BL2: Doing platform setupINFO: RAM: DDR3-DDR3L 16bits 533000kHzINFO: Memory size = 0x40000000 (1024 MB)INFO: BL2: Loading image id 1INFO: Loading image id=1 at address 0x30006000INFO: Image id=1 loaded: 0x30006000 - 0x30006236INFO: FCONF: Reading FW_CONFIG firmware configuration file from: 0x30006000INFO: FCONF: Reading firmware configuration information for: mce_configINFO: FCON

 Hello,I look for information, what is the best layout for the SMPS, which is included in the STM32H745. One of my problems is, for a proper design, you must consider to have small loops in the switching path.For my base layout, I used the same structure as it is used on the eval-kit. When I now look at the processor datasheet, I see no dedicated pins for ground, assigned to the SMPS. Where it is described to use the 3 ground pins (C16, T12, B6 on STM32H745XIH6) in this kind (Eval Kit MB1381)? These selected pins are on the opposite from the regulator. From EMC point of view, it is not really the best configuration. VSSSMPS(Pin-F2) is on the correct place, but the layout in the eval-kit is also not the best (with respect to emc) but with the three pins above, a proper groundplane underneath the processor is not possible.If someone has some documents , application notes or practical hints, I would be happy if you can share these information. My circuit, derived from the evalkit, yo

I've been looking at the information on the flash organization in the Reference manual RM0456 for STM32U5.  In particular I'm trying to understand how the DUALBANK flag works on this family.In section 7.3.1, there is this table for STM32U5G with 4MB of internal flashIn the note (1) it mentions that with DUALBANK = 1 in option bytes (which should be the default as far as I have understood), the base address for bank 2 is 0x0810_0000. But this means that bank 1 is now only 1MB.  So are the two banks overlapped?Also it is not clear to me what happens to the page size when using dual/single bank?  Is it doubled?I have seen that there is an application note for the F7 family, but I don't understand if the U5 family works the samehttps://www.st.com/resource/en/application_note/an4826-stm32f7-series-flash-memory-dual-bank-mode-stmicroelectronics.pdfCould someone please give me some additional details on how DUALBANK flag works on this family or point me to some documentati

I am having trouble to get OBK data reading working on the STM32H562 / H563 (which do not support secure storage because they are lacking hardware crypto support).My plan is to store keys in the OBK area, (encrypted with some storage key of my own) and use HDPL to make sure the application cannot access the bootloader keys.I am not really using the TrustZone, but I need to enable it in order to get HDPL support.So my secure application is very small, it configures nonsecure access for GPIO's, most of the flash (apart from the area where the secure application resides), and all IRQ's, then it jumps to my nonsecure bootloader.When I have TrustZone disabled, I can write and read OBK data like expected.As soon as I enable TrustZone, I can no longer read OBK data in my nonsecure bootloader or application, instead I'm reading all zeros.The HDP level matches the area I'm trying to read.But to be sure I'm trying to read all HDP areas, just in case I'm in an unexpected level. I expect that

Microcontroller :  STM32L476RG, External flash : AT45DB041E (4Mbit, 256 bytes of page, 2048 bytes of block),SPI2 communication protocol, using HAL.I am not able to use the LittleFS library in order to read a file that is written into the flash or any way I cannot even mount the flash. Every time I am getting the same error : (LFS_ERR_CORRUPT and after format it returns LFS_ERR_NOSPC, which is No space left on device). I don't know what it the problem I have configured some function based on the datasheet of the external flash in order to read, write and erase. I have imported the 4 basic files for littlefs into STM32CubeIDE and I don't know how to configure the cfg properly. My approach is this:  /***** LittleFS functions *****/ int block_device_read(const struct lfs_config *c, lfs_block_t block, lfs_off_t off, void *buffer, lfs_size_t size) { /*Find the physical address*/ uint32_t address = (block * c->block_size) + off + FLASH_BASE; /*Perform a

Originally a reply here: https://community.st.com/t5/stm32-mcus-touchgfx-and-gui/stm32f746g-discovery-what-is-the-difference-between-cu2-and-cu4/m-p/746537/highlight/true#M40704  - moved to a new Thread for the new question. Thank you so much for your assistance; it's working now.I would greatly appreciate your help in resolving my new issue regarding uploading the hex file using the STM32CubeProgrammer utility.Please find the attached file for your reference. Thanks and Warm Regards,Bansi Attara

I am not able to activate LWIP middleware for M7 core on any dualcore STM32. (I am able to do it on single-core devices and  already have LWIP working on H743 Nucleo)Steps I have done (exactly in this order):- create a new project for STM32H757IITx in CubeIDE- agree usage of default configuration of speculation processing- enable SYS -> Cortex_M7 -> I cache- enable SYS -> Cortex_M7 -> D cache- enable ETH and configure it for M7 core with RMII- enable FreeRTOS_M7- enable LWIP for Cortex M7 in the sidebar. Now I can see the second bar for LWIP. Runtime context M7 is checked but it is not possible to check "enable" checkbox to activate LWIP. When I put the mouse on the enable checkbox, I can see a warning that "D-cache must be enabled on M7 to use LWIP". But the problem is that D-cache is already enabled. It seems to me like a bug in IDE because I am able to activate it on singlecore devices with the exactly same steps. It also works on M4 core on dualcore H757.

In `ble_defs.h`, we have the following security permissions for attributes:/* Security permissions for an attribute */ #define ATTR_PERMISSION_NONE 0x00U /* No security. */ #define ATTR_PERMISSION_AUTHEN_READ 0x01U /* Need authentication to read */ #define ATTR_PERMISSION_AUTHOR_READ 0x02U /* Need authorization to read */ #define ATTR_PERMISSION_ENCRY_READ 0x04U /* Need encryption to read */ #define ATTR_PERMISSION_AUTHEN_WRITE 0x08U /* Need authentication to write */ #define ATTR_PERMISSION_AUTHOR_WRITE 0x10U /* Need authorization to write */ #define ATTR_PERMISSION_ENCRY_WRITE 0x20U /* Need encryption to write */In particular, we have permissions to ensure ecryption of read and write operations, but no permissions to ensure encryption for notification, indication, or write-without-response.If I create a characteristic with the write-without-response property and the encrypted write permission, then performing a write-without-response operation on that characteristic does not seem to

Hi there, I am running into trouble when tring to connect my stm32wb55 to other 3rd party peripheral. I use cubeMX and chose client profile to generate the code. Then I modified "OOB_DEMO 1" to "OOB_DEMO 0" in the app_conf.h to make the mcu start scanning automatically. The trace information shows that the scan started properly, but I cannot get any result in the case "HCI_LE_ADVERTISING_REPORT_SUBEVT_CODE". Actually, the program never go into this case.When I use p2p server profile everyting works fine, I can connect to the mcu with smart phone and exchange data. And I also can connect to 3rd party peripheral with smart phone as well, But the mcu cannot connect to the peripheral as client.

I am new to Arm but old to assembly coding (inc Toshiba 32 bit CISC - now extinct).. Just completed RCC startup code for a STM32F344 chip by looking at the 1124 pages (!) of the RM0364 manual and the CUBE LL start up code (!!!). The CUBE code has waits for: Flash latency/HSI clk/LSI clk/PLL  clk/Sysclk ready (at min). As all the waits involve the CPU in reading flash correctly to perform the wait loop, I wondered why wait?? The CPU might as well be doing something useful while it is waiting - and save some space while doing it. So I cut out all the waits. Works fine- amd code a lot smaller/neater. Yes of course everything has to settle down by the time the UART starts up and reads 250,000 baud sensibly but that is a long way down the track.So why wait?? .

We have two VL53L1X sensors side by side. Both have gilizmo cover glass and are placed 140mm from a 8.5x11 sheet of mat grey paper. Running the calibrate offset function returns 2mm for sensor one and 6mm for sensor two. Following this the Xtalk calibration function is called this returns 37333cps for sensor1 and 52562cps for sensor2. Measuring distance after calibration shows the sensors are now way off and differ 2-3 inches from each other.  My question is what could be going on to get such high values for Xtalk when we have ideal cover glass and placement?Do we want the SPAD ROI to be 16x16 when we run the calibration? currently we have it at 4x4, 200ms of timing budget, and 200ms of intermeasurement period. The sensors are in a dark room away from an external sources of IR light.  

Hi, when I generate code for the SMT32L412RBTxP using TSC with CubeMX  I get duplicated entries in tsl_user.h.One channel does not work. So I edit Channel 2 to use the missing group and IO:It now works, but when code is regenerated with CubeMX it overwrites this back to the first image.Is this a bug or am I doing something wrong?Thanks, Lance.

I connected this resonator https://jlcpcb.com/parts/componentSearch?searchTxt=C341522  And the code runs.  - however - USB fails to enumerate.If I upload the same code to a BluePill board, the code runs *and* the USB works.I suspect it being due to something is off with the resonator, and the F103 is self-oscillated.  (which would be unsupported for USB use.) How can I verify that the ceramic resonator actually is being used?  

Hi I am using the TouchGFX keyboard to input data into fields on a number of settings screens. Since the screens are small, I cannot afford the option of Cancel and Enter buttons as used in the demo. Instead I have added 2 buttons to the keyboard for Enter and Cancel. The former leaves the buffer intact, while the latter clears it before returning. However, the function that contains the keyboard container continues executing while the keyboard is in use. The result is that the data is never entered into the field. One workaround I have used is to add an 'Add/Edit' flex button  that loads the keyboard and writes the returned buffer to the model. Flex buttons over the data fields, that are made visible at the time the keyboard container is loaded, then cause the screen to reload, which then draws and displays the data from the model. It works, but it is too clunky.I have tried using a while loop to pause while the keyboard is visible, but this does nothing.Has anyone any

I have a Nucleo-H755Zi-Q and a IKS02A1. I am using the X-CUBE-MEMS1 Package. In the configurator, when I select "Board Extension IKS02A1"  I get the following error:#error "Board Pin number not defined!! Add USE_NUCLEO_144 define within stm32h7xx_nucleo_conf.h file" 61 | #error "Board Pin number not defined!! Add USE_NUCLEO_144 define within stm32h7xx_nucleo_conf.h file"#error "Board Part number not defined!! Add one of the following define within stm32h7xx_nucleo_conf.h file: USE_NUCLEO_H745ZI_Q, USE_NUCLEO_H743ZI, USE_NUCLEO_H743ZI2, USE_NUCLEO_H7A3ZI_Q, USE_NUCLEO_H723ZG" 66 | #error "Board Part number not defined!! Add one of the following define within stm32h7xx_nucleo_conf.h file:\(Without selecting "Board Extension IKS02A1" I can compile and run the code on the Nucleo-H755ZI-Q).When I add #define USE_NUCLEO_H745ZI_Q to stm32h7xx_nucleo_conf.h I get the following error:fatal error: stm32h7xx_nucleo.h: No such file or directory 31 | #include "stm32h7xx_nucleo.h" Wha

Greetings, I've been using FDCAN on STM32G0B boards at 64Mhz. I'm trying to configure an STM32H745 and it seems that the maximum clock frequency for FDCAN is 50MHz? 50Mhz itself is a very strange frequency and bitrates cannot be solved well using this frequency.With some clock tweaking I was able to get it to 48Mhz. But I wasn't able to send/receive on my FDCAN network (I'm not sure if that is related)Just looking for some thoughts on that. I am going to try 32Mhz next.

Colleagues, I have a task to accept settings and transmit measurements to the smartphone screen via USART1. The Android application is handled by a third-party company. I suspect that the task is not new, but I will have to solve it myself.For this, I want to modify the BLE_HR_p2p_Sensor project.I need to start with something small...For example, is it possible to disable the "heart rate" task through the BLE_HR_p2p_Sensor application defines.If not, I would appreciate any advice on how to painlessly disable any sensor.

Hi I'm looking for application note and design sources for STEVAL-KITXCB -Induction cooker Please share if anyone have this . Thanks

Hello Everyone,I am a beginner with STM32 (student).In TouchGFX 4.24.1 Designer, I created a simple project (two buttons and a bitmap).Then, I launch this project in STM32CubeIDE and initialize SDMMC1 and FatFS according to the AN5200 - Getting started with STM32H7 MCUs SDMMC guide. Unfortunately, I get errors, probably related to memory.When I create a project without FreeRTOS and TouchGFX, only basic handling of SDMMC1 and FatFS, everything works fine.Perhaps someone is able to help me with the correct configuration of TouchGFX + FreeRTOS + SDMMC1 on STM32H747I-DISCO or could share a working application? Thank you in advance for all the suggestions.  I have added the project as an attachment.

Hello, i need to compile example project using IAR ver. 7.40.1, (common components ver. 7.2.0), and I'm dealing with this error ".ewp was created by a newer version of the product and cannot be opened." Is there any Guide how to migrate project to older IAR version? Or set IAR compiler in CubeIDE? Thank you!

Running the iio_info command on a terminal into a STM32MP157F-DK2 (booting from the shipped SD-card) reports some errors:root@stm32mp1:~# iio_infoLibrary version: 0.23 (git tag: 92d6a35)Compiled with backends: local xml ip usb serialIIO context created with local backend.Backend version: 0.23 (git tag: 92d6a35)Backend description string: Linux stm32mp1 5.15.45 #1 SMP PREEMPT Mon Jun 6 06:43:42 UTC 2022 armv7lIIO context has 2 attributes:local,kernel: 5.15.45uri: local:IIO context has 2 devices:iio:device0: 48003000.adc:adc@0 (buffer capable)2 channels found:...ERROR: checking for trigger : Input/output error (5)iio:device1: 48003000.adc:adc@100 (buffer capable)4 channels found:...ERROR: checking for trigger : Input/output error (5)(Several dozen lines dropped here. And trying to format the output as 'code' throws HTML errors). What do these trigger - related errors tell me?If this is supposed to mean the EIO error (clib errno), i.e. a file read/write error, isn't iio_info sup

When I try to "Program and Run Target" I get the following in the log window: Compile make -f ../gcc/Makefile -j8 Reading TouchGFX/application.config Reading TouchGFX/target.config Compiling Core/Src/main.c Compiling Middlewares/Third_Party/FreeRTOS/Source/croutine.c Compiling Middlewares/Third_Party/FreeRTOS/Source/list.c Compiling Middlewares/Third_Party/FreeRTOS/Source/queue.c Compiling Middlewares/Third_Party/FreeRTOS/Source/tasks.c Compiling Middlewares/Third_Party/FreeRTOS/Source/timers.c Compiling Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c Compiling gcc/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c Core/Src/main.c:23:10: fatal error: fatfs.h: No such file or directory #include "fatfs.h" ^~~~~~~~~ compilation terminated. However, the lines in main.c around the one reported as causing the error are: /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #in

Hi,I am looking to use the STM32WL33 in a product. I am curious as to what the chip is in terms of its silicon. Is the M0+ equivalent to an available MCU?What is on the radio side? Is this an S2-LP for example?Thanks