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Greetings,I am working with nucleo_c5a3zg board and I am using zephyr RTOS for my project. I wanted to interface the sd card and try to do some data logging. I had a adafruit data logger shield which can fit on nucleo_c5a3zg board and there is a shield support in zephyr. When i build and uploaded the code i am getting a error that CMD8 is not supported. During debugging i found out that there is no state change on MISO line. Just to check if my code is wrong i tried same code with nucleo_f446re board and it works fine.Following is the capture from saleae loggic for necleo_c5a3zg board. I can provide other details like code, .dts file, etc.If someone can help me solve this issue it would be much appreciated.

I am working on an STM32N6 hardware design, and have reviewed both development kit reference designs (MB1939/MB1940). Both designs use the same power supply scheme, when using internal SMPS it has 2x 3V3 regulators and 3x 1V8 regulators.I am interested in combining several power supplies if possible, notably:1. Is it possible to tie all 3V3 together?While AN5967 suggests to apply VDD33USB in the last step of power sequencing, the VDD33USB supply is noted to be independent of the other supplies within the N6, just like the VDDIOx supplies. The reference designs have tied VDDIO4 to VDD at 3.3V, which makes me believe I could also combine VDD33USB and VDD.Aside from just VDD33USB and VDD, all the 3.3V peripherals on the dev kits come from the second 3V3 supply, can I tie all peripheral 3V3 to VDD33USB and VDD, so I have a single 3V3 rail on the PCB?If not what about the STM32N6 disallows this?2. Can I combine 1V8 for peripherals with VDD18AON?Is there anything against connecting

I’m trying to run a fork of the STM32N6-GettingStarted-ObjectDetection project for the STM32N6570-DK on my own board.My board has the same clock configuration, memory interface, and LCD interface as the STM32N6570-DK. However, instead of a CSI camera, I’m using an 8-bit parallel camera interface.The frames come from a custom FPGA source with the following parameters:75 MHz clock at 8 bit width bus YUV422 1280 × 768 30 fps Embedded synchronization ITU656My changes to the original project are:Added GPIO initialization for the 8-bit parallel camera interface. Changed the DCMIPP configuration from CSI to parallel mode:const DCMIPP_EmbeddedSyncCodesTypeDef syncСodes = { .FrameStartCode = 0xAB, /* frame SAV*/ .LineStartCode = 0x80, /* line SAV */ .LineEndCode = 0x9D, /* frame EAV */ .FrameEndCode = 0xB6 /* line EAV */};const DCMIPP_ParallelConfTypeDef pParallelConfig = { .Format = DCMIPP_FORMAT_YUV422, .VSPolarity = DCMIPP_VSPOLARITY_LOW, .HSPolarity = DCMIPP_

I’m using the MB1293 USB dongle as a daughter board for a project & am after the dimension between the 2 edge headers as I need to create a footprint on the main board. Is this information available, I’d rather not trust on manual measurement. See below,  

ST moderator: New question split from this thread: Thanks, that could indeed explain the behavior we are seeing, since we are powering Vdd with 3.3V.Since the application requires a stable ADC reference, I would like to ask whether the STM32L475 provides any internal precision reference that can be selected as the ADC conversion reference.

We are seeing different SRAM2a availability between STM32WB15CC devices with different silicon/FUS revisions.On our older STM32WB15CC devices (silicon Rev B), the device has FUS version 1.2.2.0. On these devices, BRSD_A is set, so the complete 32 KB SRAM2a region (0x20030000–0x20037FFF) is non-secure and available to CPU1.On newer STM32WB15CC devices (silicon Rev Z), we see FUS version 2.2.0.1. On these devices, the relevant configuration is:BRSD_A = 0 SBRSA_A = 0x1A Secure SRAM2a therefore starts at 0x20036800 SFSA = 0x8C, corresponding to 0x08046000 SBR = 0x1180As a result, only 26 KB of SRAM2a (0x20030000–0x200367FF) appears to be available to CPU1, while the upper 6 KB is secure.There is no wireless stack installed, and our application does not use the wireless stack/CPU2 functionality.Our existing production firmware requires the full 32 KB SRAM2a. Reducing the linker region to 26 KB is therefore not a viable workaround.This has become a production-critical issue for us: our exist

Hello,I am working with an STM32L475RET and have encountered an unexpected behavior with the ADC reference voltage.My hardware configuration is the following:VDDA and VREF+ are tied together and supplied with a precise 2.5V reference. The ADC is configured for 12-bit conversions. The 2.5V reference has been verified with a multimeter and is stable. ADC clock source is set to 48MHzWhen measuring several analog input voltages, the ADC results consistently do not match the expected values assuming a 2.5V reference. I found that the measured ADC values correspond much more closely to an effective reference voltage of approximately 2.62V rather than 2.5V. To further investigate, I measured the internal VREFINT channel and compared the ADC result against the value expected from the datasheet, and assuming a 2.5V reference, the VREFINT result (1.167V) does not match the expected value:Using this initial config for the ADC:/** * @brief ADC1 Initialization Function * @param None * @retval No

Hi ST Community,We are using the hardware CRC peripheral in our project for CRC computation.During system initialization, we initialize and configure the CRC peripheral ourselves. However, we observed that after calling MX_TouchGFX_PreOSInit(), the CRC peripheral appears to be re-initialized.We would like to understand how TouchGFX uses the CRC peripheral internally.Specifically:Does TouchGFX use the hardware CRC peripheral only during the MX_TouchGFX_PreOSInit() phase? Is the CRC peripheral used by TouchGFX during frame rendering or while processing/displaying frames? Are there any other TouchGFX phases, functions, or background operations where the CRC peripheral may be accessed? If both TouchGFX and our application use the same hardware CRC peripheral, could sharing the peripheral cause any issues?Our concern is that our application relies on a specific CRC configuration, and we want to ensure that TouchGFX does not modify or reconfigure the CRC peripheral after our initialization,

Hi,We have a project with ST25R3916B to read a NFC-B T4T card. This driver works fine.In the same state machine I am adding support for reading a NFC-A card. The `rfalNfcGetActiveDevice` correctly returns RFAL_NFC_LISTEN_TYPE_NFCA and rfalNfcaPollerCheckPresence returns RFAL_ERR_NONE, however rfalNfcaPollerFullCollisionResolution() function is returning a RFAL_ERR_TIMEOUT The Type 4B reader loop has the equivalent functions calls as the Type 4A reader and works fine, but Type 4A is having the abovementioned timeout issues with collision resolution.I am having some issues with attaching a .c file, so I will post the whole function in a comment after the question is published

Hey guys i have been using Stm32 Model Zoo repo as a base for my application development . After building a appli i want to dive deep into FSBL and optimize bootup time of stm32n6 . But the model zoo repo comes with pre compiled hex file as FSBL rather than a FSBL project . Is there any way to replace the hex file with a actual FSBL project ? 

Dear ST Support Team / Community Engineers,I am currently integrating the ST25DV04KC into my design. The VCC and LPD pins are connected to an MCU, which controls the transition between normal operation and ultra-low power mode.During testing, I observed an abnormal voltage behavior on the LPD pin:System Voltage: 3.1V Pull-up Resistor: 4.7kΩ (External) Issue: During the level switching transition, the LPD pin voltage stalls at an intermediate level of approximately 2.1V, instead of rising cleanly to VCC. This intermediate voltage persists long enough to potentially cause logic uncertainty for the MCU.Troubleshooting Steps Taken:Reduced Pull-up Resistance: I replaced the 4.7kΩ resistor with a 1.2kΩ resistor. This change successfully eliminated the intermediate voltage plateau, and the signal now transitions correctly. VCC Disconnection Test: I also noticed that disconnecting the VCC supply seems to eliminate this phenomenon as well.My Questions:What is the physical mechanism causing this

Hello everyone, I'd like to use the LevelX API with FreeRTOS on an STM32H5 microcontroller. I know that LevelX is typically used with AzureRTOS, but I'd like to know if ST provides any guidance on integrating it with FreeRTOS or if anyone has any suggestions on how I can do this. Thanks for your help.

CubeMX Version 6.18.1 (tested with STM32G491VET6) shows no "Clear Input" parameter group for TIM16/TIM17, so the OCREF-clear feature cannot be configured from the tool.The hardware does support it, per RM0440 Rev 9:§31.4.17 "Clearing the tim_ocxref signal on an external event" (TIM15/16/17 chapter) TIMx_CCMR1 bit 7 OC1CE, x = 16..17 (p. 1490) TIMx_AF2 OCRSEL[2:0], x = 16..17 (p. 1505) selecting tim_ocref_clr0..7 Table 76 "Interconnect 3": TIM16/17 ocref_clr sources include the COMP1..COMP7 outputsUse case: cycle-by-cycle peak-current limiting of a synchronous buck (COMPx clears OC1REF; CH1N provides sync-FET freewheel). For comparison, TIM1/TIM2 panes do offer "Use ETR as Clearing Source" / "Clear Input Source".Currently the only workaround is manual register writes in USER CODE (TIMx->AF2 OCRSEL + TIMx->CCMR1 OC1CE), which the .ioc cannot capture.Request: add the Clear Input group (OC1CE + OCRSEL source selection) to the TIM16/TIM17 panes for STM32G4. Image 1: Outline of RM0440

While driving PMSM motor using STM32303E-Eval with IPM20B driver card, Motor is jerking and spinning abnormaly. I am using sensored feedback method such as encoder having 1024 ppr. 

Hi!I'm struggling to wrap my head around timers - I am trying to schedule some ADC reads of a current sense amplifier in a motor control setup.I have three center-aligned PWM waveforms being generated by Timer1, which successfully commutate a BLDC motor. That's great. I would now like to schedule an ADC read once per PWM period. A simple first try at this would involve a single read right in the center of the PWM waveform. A slightly swankier version would be to calculate the largest duty cycle of my three PWM phases, and schedule my ADC read just after this point (but, again, just once per PWM period). I have experimented with configuring Timer1's TRGO to "Update Event", and scheduling my injected ADC read to be "Timer 1 Trigger Out Event". This, however, schedules the read at the beginning of the PWM period, rather than in the center of it. I'm also experimenting with setting up a slave timer - the idea being to trigger this secondary timer based on the above Timer1 TR

On cubemx I could use the scroll wheel to pan and zoom, a brilliant feature which has been removed in mx2, can we have it reinstated as the app is very frustrating to use without it

BOARD: STM32H743IITXACTICLE FOLLOWED: https://community.st.com/t5/stm32-mcus/how-to-implement-a-usb-device-composite-in-stm32h5/ta-p/708078Hello everyone,I was trying to use USB CDC+MSC in composite mode. After following the article mentioned above, i was able to build the project. But after running i was able to only get MSC (as shown in pc) and getting the CDC port with windows error 10.Few things i have changed, in usbd_desc.c updated these lines   0xEF, /* bDeviceClass */ 0x02, /* bDeviceSubClass */ 0x01, /* bDeviceProtocol */ Also i have updated CDC_IN_EP, CDC_OUT_EP, CDC_CMD_EP so it should not match MSC_EPIN_ADDR and MSC_EPOUT_ADDR     #ifndef CDC_IN_EP #define CDC_IN_EP 0x82U /* EP1 for data IN */ #endif /* CDC_IN_EP */ #ifndef CDC_OUT_EP #define CDC_OUT_EP 0x02U /* EP1 for data OUT */ #endif /* CDC_OUT_EP */ #ifndef CDC_CMD_EP #define CDC_CMD_EP 0x83U /* EP2 for CDC commands */ #endif /* CDC_CMD_EP */ #ifndef MSC_EPIN_ADDR #define MSC_EP

On the STM32C542RC, this is my current FLASH layout:-- OEMiRoT flash layout:-- Bootloader : 0x08000000 .. +0x10000-- Keys : +0x10000 (0x2000)-- NV counters : +0x12000 (0x2000)-- Primary app slot : 0x8014000 size=0x16000-- App code (post-hdr) : 0x8014400 size=0x15c00-- Secondary app slot : 0x802a000 size=0x16000-- OEMiRoT option bytes to program:-- HDP1_END = 0x9 WRPSGn1 = 0xfe00Everything is working well (update of user application, boot, etc...) (MCUBOOT_USE_HASH_REF is not defined).But I have an issue:I want to use the external User Data Flash at the address FLASH_EXT_USER_BASE 0x08400000UL, requiring the option byte EDATA_EN = 0. When I read from that address in the User Application, I only read zeroes (RAZ) -- simple as `*(const int *)FLASH_EXT_USER_BASE == 0`, so this feels like the cause is some sort of HDP. By the way, the writes do work (at least when the MCU is reset, as STM32CubeProgramm

I was trying to configure ethernet on my android phone via using usb cdc ncm on stm32 nucleo U5A5 and i was unable to see the ethernet option in the network settings of the phone.It was completely greyed out. I tried the same on ios and i was able to connect via ethernet. What am i supposed to do to resolve this ?im using ncm of tiny usb for this connectivity.

Hello,I am using an STM32F207VC custom board with Ethernet and LwIP. I am facing an issue related to Ethernet cable connection during power-up.I performed the following tests:Test A: Ethernet cable connected before power ONConnect the Ethernet cable.Power ON the STM32 board.Result:Ping: WorkingTCP server connection: WorkingTest B: Ethernet cable disconnected during power ONDisconnect the Ethernet cable.Power ON the STM32 board.Wait until all STM32, Ethernet, and LwIP initialization is completed.Connect the Ethernet cable.Result:PHY Link Up: DetectedPing: WorkingTCP server connection: Not workingTest C: Cable disconnect and reconnect after normal startupStart the board with the Ethernet cable connected.TCP server works normally.Disconnect the Ethernet cable.Reconnect the Ethernet cable.Result:Ping: WorkingTCP server connection: WorkingThe issue occurs only when the STM32 board is powered ON while the Ethernet cable is disconnected and the cable is connected later.Since ping works and th

  When enabling USB_OTG_FS peripheral in Device_Only mode for STM32H743VIT6, CubeMX generates usb_otg.c with incorrect HAL macros:Generated (wrong) Should be (H7-native) GPIO_AF10_OTG1_FS GPIO_AF10_OTG2_FS __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB2_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB2_OTG_FS_CLK_DISABLE  Root cause:  On STM32H7, the FS USB peripheral is USB2_OTG_FS, not USB1_OTG_FS. The H7 HAL defines GPIO_AF10_OTG2_FS for the FS port and GPIO_AF10_OTG1_HS for the HS port. CubeMX, however, generates F4/F7-style macro names (e.g. GPIO_AF10_OTG1_FS) which are only valid for MCUs with a single USB OTG peripheral.  Moreover, GPIO_AF10_OTG1_FS is conditionally defined in stm32h7xx_hal_gpio_ex.h only when USB2_OTG_FS is not defined. Since STM32H743 does define USB2_OTG_FS, the macro is absent at compile time.  The legacy compatibility aliases in stm32_hal_legacy.h could resolve this, but CubeMX does not include that header in the generated code.No

Hi, I wrote a flash bootloader for STM32G070 using IAR ide.It gets via modbus RTU the command/data to manage the FSM that does the update procedure.Because the master during erasing/programming needs a real time update on overall progression, the .intvec table, the main, the modbus stack and the updaing FSM are all relocated in RAM.With firmware in RAM and a management of FLASH delete/program via IT the firmware can handle modbus during flash programming.The .intvec relocation is done programmtically, copying it from FLASH (0x08000000) to RAM (0x20000000)  (0xB8 bytes):  I did via explicit firmware because I’m not able to do it via .icfAlso relocated in RAM  stm32g0xx_hal_flash*.o via “initialize by copy” in .icf.VTOR set to 0x20000000main entry point and other self-made function as well as modbus stack’s  marked as __ramfunc.Great, you say, if everyhing works why this topic? The truth is: to do all above I did a workaround  because a problem came when I linked HAL_FLASH_IRQHandler.Wit

Can we flash same hex file in STM32xxxxVJT6 and STM32xxxxVJT3.

Hi, I have been trying to implement the L6983 in my design for about 4 month now and still don’t get the desired output. After checking the Fsw pin, it seems I don’t get any clock output, do you have any idea what would be the cause of this issue ? Here is m design.The 0Ohm strips are only for a backup power supply. The Fsw output is flat on GND at the oscilloscope.The SW output before the inductor is at my supply voltage of 28V with small disconnects resulting in a flat 28V after the inductor.The input is 28V and it should output 5.2VThe switching method should be 500kHz without ditheringVs is delivered by a L6981 power supply + L39200 LDO at 3V3. This issue is present on several iterations of this design even though we made sure to reference the ST eDesign Suite for our choices.

Part Number: STM32F427VIT6Environment: Custom PCB (not an eval/dev board), native SDIO/SDMMC1 peripheral, 4-bit bus, FatFs (ChaN's ff.c) on top of ST's HAL (stm32f4xx_hal_sd.c). STM32CubeIDE 2.2.0, GNU Arm Embedded toolchain 14.3.rel1 (arm-none-eabi-gcc), STM32CubeProgrammer for flashing/SWD debug, bare-metal HAL (no RTOS). SDIO clock tested from 400kHz up to ~24MHz; same result throughout.Schematics / hardware note: This is a custom PCB, so a board-level cause can't be fully excluded, a scope check on the 3.3V rail during a write burst is still pending, and I'm happy to attach the relevant SDMMC1/power schematic on request. That said, a pure PCB signal-integrity/trace defect looks unlikely specifically: DAT0-3 are bidirectional and reads over those same physical traces are 100% reliable, every write's CRC check passes cleanly, the failure is fully deterministic rather than marginal/intermittent, and it's unchanged across the full 400kHz-24MHz clock range tested, none of that fits a ti