Posted on October 09, 2017 at 14:18 I’m trying to understand STM8 pipelining to be able to predict how much cycles my code will need.
(I already
https://stackoverflow.com/questions/46629607/understanding-stm8-pipelining
, but I figured this focum is probably the better audience).
I have this example, where I toggle a GPIO pin for 4 cycles each. Iffloopis aligned at 4byte-boundary + 3, the pin stays active for 5 cycles (i.e. one more than it should). I wonder why?
// Switches port D2, 5 cycles high, 4 cycles low void main(void) { __asm bset 0x5011, #2 ; output mode bset 0x5012, #2 ; push-pull bset 0x5013, #2 ; fast switching jra _loop .bndry 4 nop nop nop _loop: nop bset 0x500f, #2 nop nop nop bres 0x500f, #2 jra _loop __endasm; }
A bit more context:
- bset/bresare 4 byte instructions,nop1 byte.
- Thenop/bset/bresinstructions take 1 cycle each.
- Thejrainstruction takes two cycles. I think in the first cycle, the instruction cache is filled with the next 32bit value, i.e. in this case thenopinstruction only. And the 2nd cycle is actually just the CPU being stalled while decoding the next instruction.
So in cycles:
- bresclears the pin
- jra, pipeline flush,nopfetch
- nopdecode,bsetfetch
- nopexecute,bsetdecode, nextnopfetch
- bsetexecute sets the pin
- nop,bresfetch
- nop
- nop,bresdecode
- bresexecute clears the pin
According to this, the pin should stay LOW for 4 cycles and HIGH for 4 cycles, but it’s staying HIGH for 5 cycles.
In any other alignment case, the pin is LOW/HIGH for 4 cycles as expected.
I think, if the PIN stays high for an extra cycle that must mean that the execution pipeline is stalled after thebsetinstruction (thenops thereafter provide enough time to make sure thatbreslater is ready to execute immediately). But according to my understandingnop(for 6.) would already be fetched in 4.
Any idea how this behavior can be explained? I couldn’t find any hints in the
http://www.st.com/content/ccc/resource/technical/document/programming_manual/43/24/13/9a/89/df/45/ed/CD001617pdf/files/CD001617pdf/jcr:content/translations/en.CD001617pdf
.
#cpu #cycle #pipelining #performance
