STM8S103 Timer TIM2 timing

[sthvw]

Hi,

Using ST Workbench debugger my 16-bit timer TIM2 (china bought) overflows each 16 seconds as the prescaler is set to 10. With an 16MHz internal clock divided by 2^10 (1024) the timer should overflow theoretically each 4.1 seconds. Prescaler 9 takes 8 seconds an prescaler 8 takes 4 seconds. So it is consistent but not according documentation. Where do I go wrong? Or is the internal clock 4MHz???

[Peter BENSCH]

Unfortunately, you have not shown the relevant program parts of the initialisation of the clock tree. The timers are clocked by fMASTER (see RM0016, section 9), which in turn can be derived from fHSIDIV. fHSIDIV in turn is the 16MHz clock HSI divided by 1/2/4/8. You have probably set HSIDIV to 1/4?

Regards
/Peter