https://www.st.com/en/evaluation-tools/stdes-viennarect.html
I have some questions about the PDF "stdes-vienna rect" that can be obtained from "Download data brief" in.
1) Why is the CCO_clk on page 4 connected to DIGIN [1] and DIGIN [2]? Does it make sense to recapture the clock I generated?
Is it a wiring mistake?
2) "Vdc_ref" in Figure 1 on the 3rd page is not found as far as the wiring of the CPU on the 4th page is seen. How do you instruct the CPU?
Is it a fixed value written in the CPU?
3) The elements required for "Voltage Control" in Figure 1 on page 3 are "Vdc_ref", "ADC3 (V_bus_up)", and "ADC4 (Oout)", but the elements required for "Voltage Control" are Oout (ADC4). Isn't it V_bus_down (ADC2) instead of)?
If V_bus_down is the correct answer instead of Oout, is it Figure 1 or the CPU wiring on page 4 that is wrong?
4) I may not understand because it is abbreviated as "power board: gate drivers (x6)" in Figue 10 on page 11. There are 6 "SCTW35N65G2V", but there are only 3 PWMs to control "STGAP2SM": "PWM_INP_Q1", "PWM_INP_Q2" and "PWM_INP_Q3". I thought that "GATE L" and "GATE R" would move in the same way, but then "GATE L" and "GATE R" are controlled separately because there is no need to have six "STGAP2SM". Is it?
5) It is "TEMP" in the CPU wiring on the 4th page, but is it a mechanism that does not output "REF_SIN" if there is no value here?
If anyone knows, I would appreciate it if you could answer.
Thank you.
