STM32N6 SDRAM CLK is inactive

[TheImmortal]

Hello,
I cant start SDRAM to work, I ques what FMC controller do not initialize interface correctly because CLK is dead (bug !?), there is no activity at all, I connected oscilloscope to CLK output to check, if I toggle manually the pin PD9 (FMC_SDCLK) is changing state, there is no difference what frequency is set and what is RCC source, now CLK is set to 50Mhz, source IC4 100Mhz, similar code on H7 works without problems even if frequency is to high for my SDRAM 143Mhz (tested - works well up to ~165Mhz), there is initialization code:

static void MX_FMC_Init(void){
  /* USER CODE BEGIN FMC_Init 0 */
  /* USER CODE END FMC_Init 0 */
  FMC_SDRAM_TimingTypeDef SdramTiming = {0};
  /* USER CODE BEGIN FMC_Init 1 */
  /* USER CODE END FMC_Init 1 */
  /** Perform the SDRAM1 memory initialization sequence  */
  hsdram1.Instance = FMC_SDRAM_DEVICE;
  /* hsdram1.Init */
  hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
  hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
  hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
  hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
  hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
  hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
  hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
  hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
  hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_2;
  /* SdramTiming */
  SdramTiming.LoadToActiveDelay = 2;
  SdramTiming.ExitSelfRefreshDelay = 7;
  SdramTiming.SelfRefreshTime = 4;
  SdramTiming.RowCycleDelay = 7;
  SdramTiming.WriteRecoveryTime = 3;
  SdramTiming.RPDelay = 2;
  SdramTiming.RCDDelay = 2;

  if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK){
    Error_Handler( );
  }
  /* USER CODE BEGIN FMC_Init 2 */
  //-----------------------------------------------------------------------------------
   FMC_SDRAM_CommandTypeDef Command;
    Command.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE; /* Set MODE bits to "001" */
    Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1; /* configure the Target Bank bits */
    Command.AutoRefreshNumber      = 1;
    Command.ModeRegisterDefinition = 0;
    HAL_SDRAM_SendCommand(&hsdram1, &Command, 0xfff);
    HAL_Delay(1); /* Step 4: Insert 100 us minimum delay - Min HAL Delay is 1ms */

    Command.CommandMode            = FMC_SDRAM_CMD_PALL; /* Set MODE bits to "010" */
    Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1; /* configure the Target Bank bits */
    Command.AutoRefreshNumber      = 1;
    HAL_SDRAM_SendCommand(&hsdram1, &Command, 0xfff);

    Command.CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE; /* Set MODE bits to "011" */
    Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1; /* configure the Target Bank bits */
    Command.AutoRefreshNumber      = 2; // 2 8
    HAL_SDRAM_SendCommand(&hsdram1, &Command, 0xfff);

    Command.CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;/*set the MODE bits to "100" */
    Command.CommandTarget		   = FMC_SDRAM_CMD_TARGET_BANK1;
    Command.AutoRefreshNumber      = 1;
    //Command.ModeRegisterDefinition =  (uint32_t) SDRAM_MODEREG_BURST_LENGTH_1 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | SDRAM_MODEREG_CAS_LATENCY_3 | SDRAM_MODEREG_OPERATING_MODE_STANDARD | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
    Command.ModeRegisterDefinition = (uint32_t)0 | 0<<3 | 2<<4 | 0<<7 | 1<<9;
    HAL_SDRAM_SendCommand(&hsdram1, &Command, 0xfff);

    uint32 freqsdrm = (50000 * 64 / 8192) - 20;
    HAL_SDRAM_ProgramRefreshRate(&hsdram1, freqsdrm); // 2058 = 133, 1933 1542

  /* USER CODE END FMC_Init 2 */
}

[TheImmortal]

I found the problem, in HAL_SDRAM_Init() function the SDRAM control registers for SDRAM device 1 (FMC_SDCR1) the bit 16 (SDEN) is not enabled/set in function, you have to enable to get FMC to work, but still there is some problem with frequency, I have set IC14 to 280 and FMC SDRAM common clock to 2, but SDCLK output is only 8Mhz !  With H7 mcu I dont had such problems !
This MCU is good, but SW is full of bugs !

[Ghofrane GSOURI]

Hello @TheImmortal 

Regarding the first point " Missing code for enabling the SDEN " , an internal Ticket 218981 has been raised to our dev team  for further investigation.

For the second point, could you please provide your IOC file? This will allow me to review your configuration in detail and help identify the cause of the issue.

THX

Ghofrane

[Ghofrane GSOURI]

Hello @TheImmortal 

I am sharing with you the explanation provided by our expert:

The SDEN bit is set in the SystemInit_ExtMemCtl() function, which is called by SystemInit().

Indeed, FMC_SDRAM_DataMemory() is an advanced example that shows to the customer how to bypass the internal SRAM and how to use only the SDRAM available on the external memory.

This is why, BEFORE entering main(), the SDRAM is fully initialized and enabled by direct register accesses, done in SystemInit().

Once the code starts executing in main(), the SDRAM is up and running and replaces the internal SRAM.

And this is why the initialization must be done as early as possible.
Since CubeMX does not automatically generate a call to SystemInit_ExtMemCtl(), you should manually add the following line of code:
FMC_Bank5_6_R->SDCR[0] |= FMC_SDCRx_SDEN;

THX

Ghofrane

[TheImmortal]

Hello,

I dont searched for solution to replace, it's about additional memory for camera stream, and until I do not enabled manually SDEN bit the CLK do not worked !

And about you comment "The SDEN bit is set in the SystemInit_ExtMemCtl() function, which is called by SystemInit()." - you talking what SDEN is enabled ?

"you should manually add the following line of code" (I did and got CLK running):
FMC_Bank5_6_R->SDCR[0] |= FMC_SDCRx_SDEN;" !

About frequency - the sysclk init is in FSBL, and there is no additional check and initialization in APPLI, and there is the reason why I do not got required frequency for SDRAM and some other peripheries, I debugging directly by uploading and starting APPLI, and because FSBL is bypassed the sysclk clocks was left unset and was run on default frequencies, my solution for debugging - just copy paste init function.

[Ghofrane GSOURI]

Hello @TheImmortal 

Can you please confirm if my understanding is correct?

When you run the full boot sequence (FSBL → APPLI), the system clock is initialized by the FSBL, and everything works as expected.
However, when you debug or run the APPLI directly (bypassing the FSBL), the SystemClock_Config() function is never called. As a result, the MCU operates at its default clock settings, which are usually much lower than required for SDRAM and other peripherals. This causes the SDRAM clock (SDCLK) to be incorrect or inactive, leading to initialization failures.

Therefore, to ensure proper operation in all scenarios, SystemClock_Config() should be present and called in both the FSBL and APPLI contexts.

Ghofrane

[TheImmortal]

Hello,

Yes, if I run full boot sequence everything works fine, but then bypassing FSBL the clock frequencies is at default, I found what SystemClock_Config() does not exist in APPLI, I simply copied form FSBL and now works good.

And I have some similar issue with ADC DMA, even if is not used and disabled (unchecked) in FSBL, if I run directly APPLI and bypassing FSBL then DMA do not work, if trying to start I getting busy error, and there is same - if I run full sequence the ADC DMA works as expected.