FAQ: STM32MP1 how to validate the STM32MP1-DRAM connection on PCB, DDR test suite

[Emmanuel COMBETTE DE RYMON]

What is the method to validate the STM32MP1-DRAM path on your PCB ?
Is manual DDR PHY tuning using STM32CubeMX DDR tuning still needed ?
Where to find the DDR test suite binary and the relative documentation to run the tests ?

ST, to help the PCB designer, provides different documents like AN5122 layout recommendation and examples,  see more with https://community.st.com/s/article/FAQ-STM32MP1-What-ST-offers-to-make-a-PCB-design-that-ensures-signal-integrity

1. DDR test suite for the PCB validation.

In majority of the designs, the DDR tests suite pass as soon as the designer carefully respects the AN5122 Layout constraints (at condition there is no error in the schematics nor in the layout).
Passing the DDR tests is main criteria to validate the platform in the whole STM32MP1 temperature range for DDR3L or LPDDR memory types.
It is recommended at bring-up phase to test your platform with the DDR test suite.
In case of suspicious failures in application, a sanity check 'time margin' procedure is available https://drive.google.com/file/d/1Dh6jFb2rsjWcGXMupsuK4UVD33Y6OnmP/view?usp=sharing

2. Manual DDR PHY Tuning is deprecated

Along with the DDR setup and the DDR tests in STM32CubeMx, the DDR PHY tuning was also supported. But it become deprecated in ecosystem 3.X and is removed in the 4.X ecosystem release. ST experienced that DDR PHY fine tuning can be avoided as it brings negligible delay. The important fact is that the AN5122 is correctly respected. Manual DDR PHY tuning over different boards is not necessary.
To simplify, this manual PHY tuning is replaced by automatic DDR build-in PHY tuning at boot time. For this,TF-A enables the DDR-PHY buil-in DQS training (aka DQSTRN).
Since ecosystem 3.1.0 and 2.1.x latest, the Read Valid Training (aka RVTRN) is also enabled for LPDDR DRAMs at very low temperatures.
Since ecosystem 4.0  it is strongly recommended to use automatic DDR-PHY built-in tuning by removing the "st,phy-cal" property in TF-A device tree (dtb).
https://wiki.st.com/stm32mpu/wiki/DDRCTRL_and_DDRPHYC_device_tree_configuration#st-2Cphy-cal_value_and_DDR_tuning.
Automatic DDR PHY tuning is enabled when TF-A log shows up:  “WARNING: Couldn't find property st,phy-cal in dtb”
This property is deprecated, the DDR-PHY built-in tuning is always enabled in the 4.X ecosystem release.
 

3. Where to get the DDR test suite binary

 
DDR test suite code was located Uboot SPL binary under the  "basicboot" Uboot configuration.
 
Since 4.X ecosystem, the DDR tests are moved in a new STM32DDRFW-UTIL STM32CubeIDE project. The DDR test suite allow to test the memory setting file that will be used later on in TF-A.

The DDR tests binary is loaded via JTAG on STM32MP1 in engineering boot mode. Alternatively It can be loaded with STM32CubeProgrammer CLI commands on an UART console or alternatively from STM32CubeMX DDR test suite view. In both case DDR test can be run under a Windows PC. 
 

 4. Where to get the DDR test documentation

 
-Under https://wiki.st.com/stm32mpu/wiki/Category:STM32DDRFW-UTIL
you can get github project and documentation about how to run the test.
-The STM32CubeMX UM1718 show the device tree files generation to configure the STM32MP1 DDR controller. It give also all instructions to run the DDR tests. Accurate details about STM32MP1 DDR Controller and about STM32CubeMX DRAM configuration parameters in AN5168.
Additional resources :
-https://community.st.com/s/article/FAQ-STM32MP1-Bring-up-procedure