The processor in this application is an STM32MP153. I'm using a Cypress FX3 emulating SRAM so I can use a read path of FMC->MDMA->AXI memory-to-memory and vice versa for the write path. Two independent hardware interrupts on the STM32 GPIOs initiate the relevant transfers (MDMA initiation is via software only).
My question relates to the variable data size inherent in the FX3 state machine. What is the advisable method to accommodate this in the STM32MP153?
a) set up multiple stream definitions for the MDMA and use extra GPIOs to semaphore the buffer sizes between the processors?
b) keep block transfers consistent and have the CPU analyse the result and then drop in a circular link list buffer for isochronous data transfers? (I'm not yet clear on whether the A7 CPUs will have the time to set this up before the full bandwidth data consumption is demanded).
c) neither of the above - there's an alternative referred/recommended approach.
Note that:
1) A0 is the only address pin used to semaphore the FX3. All other address lines are irrelevant.
2) data transfer width is 16b, AXI width is 16b, STM32MP153 SRAM data width is 16b (alternatively to/from 512MB/1GB of DDR3L)
3) STM32MP153 DMA1/2 are not fast enough (on paper) via the AHB (do tell me otherwise)
I'd appreciate all suggestions as I'm at the schematic stage at the moment and have all options open to the design.
Thank you for reading.
