I'm bringing up a very simple board that uses STM32MP135 with LAN8742A-CZ-TR Ethernet PHY as on the eval board. Unlike the eval board, however, I clock the PHY directly from the SoC: PA11/ETH1_CLK from the STM32 is connected to XTAL1/CLKIN on the PHY.
I obtained the drivers from the STM32CubeMP13 package (version 1.2.0, or GitHub commit 0ef689b06775da063006da84d952d8bd48f9e5e1). Since I'm not making use of the ETH1_RX_CLK, I tell the HAL to source the 50MHz clock directly from the RCC:
eth_handle.Init.ClockSelection = HAL_ETH1_REF_CLK_RCC;
The Ethernet driver in stm32mp13xx_hal_etc.c (correctly) makes use of this information to set a bit in the PMCSETR register:
if (heth->Init.ClockSelection == HAL_ETH1_REF_CLK_RCC)
{
syscfg_config |= SYSCFG_PMCSETR_ETH1_REF_CLK_SEL;
}
HAL_SYSCFG_ETHInterfaceSelect(syscfg_config);
However, later on, an assertion fails which does not expect the RCC bit to be set in this register:
#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH1_MII) || \
((CONFIG) == SYSCFG_ETH1_RMII) || \
((CONFIG) == SYSCFG_ETH1_RGMII) || \
((CONFIG) == SYSCFG_ETH2_MII) || \
((CONFIG) == SYSCFG_ETH2_RMII) || \
((CONFIG) == SYSCFG_ETH2_RGMII))
If I simply comment out this assertion check, the code appears to work fine. But now I'm worried that something else will break. Is there a good reason that the above macro only permits setting the ETH1/ETH2 interfaces, and none of the other bits in this register? Or can I just comment out this check, as I had done?
For more details about my board and Ethernet bring-up, see this blog post.
