Failed to init the clock at STM32MP257: What is clock ID 5?

DMårt · ‎2026-02-07

I got a panic message from drivers/st/clk/clk-stm32-core.c at Trusted Firmware.

My question is: What is clock ID 5? Is that MSI clock or LSE clock?

Is there any information I could read about this ID?

int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
{
	const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);

	if ((ops->is_enabled != NULL) && ops->is_enabled(priv, id)) {
		return 0;
	}

	if (ops->enable != NULL) {
		ops->enable(priv, id);
	}

	if ((ops->is_enabled != NULL) && !ops->is_enabled(priv, id)) {
		ERROR("failed to enable clock id: %u\n", id);
		panic();
	}

	return 0;
}

The output is

NOTICE:  Early console setup
ERROR:   failed to enable clock id: 5
BACKTRACE: START: clk_stm32_enable_call_ops
0: EL3: 0xe017bac
1: EL3: 0xe01be2c
2: EL3: 0xe01beb0
3: EL3: 0xe01bf54
4: EL3: 0xe01c240
5: EL3: 0xe01db28
6: EL3: 0xe029a2c
7: EL3: 0xe0170dc
BACKTRACE: END: clk_stm32_enable_call_ops
PANIC at PC : 0x000000000e01be34

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer

STM32MP257FAK3 custom board with STM64-OS as operating system: https://github.com/DanielMartensson/STM64-Computer

PatrickF · ‎2026-02-08

Hi @DMårt

maybe HSE oscillator not starting ?

https://github.com/STMicroelectronics/arm-trusted-firmware/blob/v2.10-stm32mp/include/dt-bindings/clock/stm32mp15-clks.h

Regards.

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DMårt · ‎2026-02-09

@PatrickF

It's for STM32MP257, not STM32MP157.

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer

STM32MP257FAK3 custom board with STM64-OS as operating system: https://github.com/DanielMartensson/STM64-Computer

PatrickF · ‎2026-02-09

Sorry for mixed-up.

So, definitely not I2S_CLK as per https://github.com/STMicroelectronics/arm-trusted-firmware/blob/v2.10-stm32mp/include/dt-bindings/clock/stm32mp25-clks.h

Probably not MSI (which is internal).

It could be LSE (e.g. fail to start oscillator), but not sure it is used in TF-A.

Are you sure about HSE oscillation and setup in DT ?

Regards

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
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DMårt · ‎2026-02-09

@PatrickF

It seems that LSE and HSE is disabled already in TF-A. I'm guessing that it could be some settings in DT tyst should be default in CubeMX, but it isin't.

 * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
 */

/dts-v1/;

#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/clock/stm32mp25-clksrc.h>
#include "stm32mp25-mx.dtsi"

#include "stm32mp257.dtsi"
#include "stm32mp25xf.dtsi"
#include "stm32mp257f-firmware-mx-rcc.dtsi"
#include "stm32mp25xxak-pinctrl.dtsi"
#include "stm32mp25-ddr.dtsi"

/* USER CODE BEGIN includes */
/* USER CODE END includes */

/ {
        model = "STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11";
        compatible = "st,stm32mp257f-firmware-mx", "st,stm32mp257";

        memory@80000000 {
                device_type = "memory";
                reg = <0x0 0x80000000 0x00000001 0x00000000>;

                /* USER CODE BEGIN memory */
                /* USER CODE END memory */
        };

        /* USER CODE BEGIN root */

        aliases{
                serial0 = &usart2;
        };

        chosen{
                stdout-path = "serial0:115200n8";
        };

        /* USER CODE END root */

}; /*root*/

&pinctrl {
        i2c7_pins_mx: i2c7_mx-0 {
                pins {
                        pinmux = <STM32_PINMUX('D', 14, AF10)>, /* I2C7_SDA */
                                         <STM32_PINMUX('D', 15, AF10)>; /* I2C7_SCL */
                        bias-disable;
                        drive-open-drain;
                        slew-rate = <0>;
                };
        };

        sdmmc1_pins_mx: sdmmc1_mx-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */
                                         <STM32_PINMUX('E', 1, AF10)>, /* SDMMC1_D3 */
                                         <STM32_PINMUX('E', 2, AF10)>, /* SDMMC1_CMD */
                                         <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
                                         <STM32_PINMUX('E', 5, AF10)>; /* SDMMC1_D1 */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <1>;
                };
                pins2 {
                        pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <3>;
                };
        };

        usart2_pins_mx: usart2_mx-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('A', 15, AF6)>; /* USART2_RX */
                        bias-disable;
                        drive-push-pull;
                };
                pins2 {
                        pinmux = <STM32_PINMUX('C', 1, AF6)>; /* USART2_TX */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <0>;
                };
        };

        /* USER CODE BEGIN pinctrl */
        /* USER CODE END pinctrl */
};

&pinctrl_z {
        /* USER CODE BEGIN pinctrl_z */
        /* USER CODE END pinctrl_z */
};

&bsec {
        status = "okay";

        /* USER CODE BEGIN bsec */
        board_id: board_id@3d8 {
                reg = <0x3d8 0x4>;
        };
        /* USER CODE END bsec */
};

&ddr {
        status = "okay";

        /* USER CODE BEGIN ddr */
        vdd1-supply = <&vdd1_ddr>;
        vdd2-supply = <&vdd2_ddr>;
        vddq-supply = <&vdd2_ddr>;
        /* USER CODE END ddr */
};

&i2c7 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c7_pins_mx>;
        status = "okay";

        /* USER CODE BEGIN i2c7 */
        i2c-scl-rising-time-ns = <185>;
        i2c-scl-falling-time-ns = <20>;
        clock-frequency = <400000>;
        #address-cells = <1>;
        #size-cells = <0>;

        pmic2: stpmic@33 {
                compatible = "st,stpmic2";
                reg = <0x33>;
                status = "okay";

                regulators {
                        compatible = "st,stpmic2-regulators";

                        vddcpu: buck1 {
                                regulator-name = "vddcpu";
                                regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <910000>;
                                regulator-always-on;
                        };
                        vddcore: buck2 {
                                regulator-name = "vddcore";
                                regulator-min-microvolt = <820000>;
                                regulator-max-microvolt = <820000>;
                                regulator-always-on;
                        };
                        vddgpu: buck3 {
                                regulator-name = "vddgpu";
                                regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <900000>;
                                regulator-always-on;
                        };
                        vddio_pmic: buck4 {
                                regulator-name = "vddio_pmic";
                                regulator-min-microvolt = <3300000>;
                                regulator-max-microvolt = <3300000>;
                                regulator-always-on;
                        };
                        v1v8: buck5 {
                                regulator-name = "v1v8";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
                                regulator-always-on;
                        };
                        vdd2_ddr: buck6 {
                                regulator-name = "vdd2_ddr";
                                regulator-min-microvolt = <1100000>;
                                regulator-max-microvolt = <1100000>;
                        };
                        v3v3: buck7 {
                                regulator-name = "v3v3";
                                regulator-min-microvolt = <3300000>;
                                regulator-max-microvolt = <3300000>;
                                regulator-always-on;
                        };
                        vdda1v8_aon: ldo1 {
                                regulator-name = "vdda1v8_aon";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
                                regulator-always-on;
                        };
                        vdd_emmc: ldo2 {
                                regulator-name = "vdd_SD_card_temporary";
                                regulator-min-microvolt = <3300000>;
                                regulator-max-microvolt = <3300000>;
                                regulator-always-on;
                        };
                        vdd1_ddr: ldo3 {
                                regulator-name = "vdd1_ddr";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <1800000>;
                        };
                        vdd3v3_usb: ldo4 {
                                regulator-name = "vdd3v3_usb";
                                regulator-min-microvolt = <3300000>;
                                regulator-max-microvolt = <3300000>;
                                regulator-always-on;
                        };
                        v5v_hdmi: ldo5 {
                                regulator-name = "v5v_hdmi";
                                regulator-min-microvolt = <2000000>;
                                regulator-max-microvolt = <2000000>;
                        };
                        vdd_sdcard: ldo7 {
                                regulator-name = "vdd_sdcard";
                                regulator-min-microvolt = <3300000>;
                                regulator-max-microvolt = <3300000>;
                                regulator-always-on;
                        };
                        vddio_sdcard: ldo8 {
                                regulator-name = "vddio_sdcard";
                                st,regulator-bypass-microvolt = <3300000>;
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <3300000>;
                                regulator-always-on;
                        };
                };
        };
        /* USER CODE END i2c7 */
};

&icache {
        status = "okay";

        /* USER CODE BEGIN icache */
        /* USER CODE END icache */
};

&rcc {
        status = "okay";

        /* USER CODE BEGIN rcc */
        /* USER CODE END rcc */
};

&sdmmc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&sdmmc1_pins_mx>;
        status = "okay";

        /* USER CODE BEGIN sdmmc1 */
        st,neg-edge;
        bus-width = <4>;
        vmmc-supply = <&vdd_sdcard>;
        vqmmc-supply = <&vddio1>;
        /delete-property/cap-sd-highspeed;
        /delete-property/cap-mmc-highspeed;
        /* USER CODE END sdmmc1 */
};

&usart2 {
        pinctrl-names = "default";
        pinctrl-0 = <&usart2_pins_mx>;
        status = "okay";

        /* USER CODE BEGIN usart2 */
        /* USER CODE END usart2 */
};

/* USER CODE BEGIN addons */
/* USER CODE END addons */

 * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration 
 */ 

&clk_lsi { 
        clock-frequency = <32000>; 

        /* USER CODE BEGIN clk_lsi */ 
        /* USER CODE END clk_lsi */ 
}; 
&clk_hsi { 
        clock-frequency = <64000000>; 

        /* USER CODE BEGIN clk_hsi */ 
        /* USER CODE END clk_hsi */ 
}; 
&clk_msi { 
        clock-frequency = <16000000>; 

        /* USER CODE BEGIN clk_msi */ 
        /* USER CODE END clk_msi */ 
}; 
&clk_lse { 
        status = "disabled"; 

        /* USER CODE BEGIN clk_lse */ 
        /* USER CODE END clk_lse */ 
}; 
&clk_hse { 
        status = "disabled"; 

        /* USER CODE BEGIN clk_hse */ 
        /* USER CODE END clk_hse */ 
}; 

&rcc { 

        st,flexgen = < 

                FLEXGEN_CFG(0, XBAR_SRC_HSI, 0, 0) 
                FLEXGEN_CFG(1, XBAR_SRC_HSI, 0, 0) 
                FLEXGEN_CFG(2, XBAR_SRC_HSI, 0, 0) 
                FLEXGEN_CFG(3, XBAR_SRC_HSI, 0, 0) 
                FLEXGEN_CFG(4, XBAR_SRC_HSI, 0, 0) 
                FLEXGEN_CFG(5, XBAR_SRC_HSI, 0, 0) 
                FLEXGEN_CFG(6, XBAR_SRC_HSI, 0, 0) 
                FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) 
                FLEXGEN_CFG(15, XBAR_SRC_HSI_KER, 0, 0) 
                FLEXGEN_CFG(33, XBAR_SRC_HSI_KER, 0, 0) 
                FLEXGEN_CFG(43, XBAR_SRC_HSI_KER, 0, 24) 
                FLEXGEN_CFG(44, XBAR_SRC_HSI_KER, 0, 7) 
                FLEXGEN_CFG(45, XBAR_SRC_HSI_KER, 0, 3) 
                FLEXGEN_CFG(51, XBAR_SRC_HSI_KER, 0, 0) 
                FLEXGEN_CFG(63, XBAR_SRC_HSI_KER, 0, 0) 
        >; 

        st,busclk = < 
                DIV_CFG(DIV_LSMCU, 0) 
                DIV_CFG(DIV_APB1, 0) 
                DIV_CFG(DIV_APB2, 0) 
                DIV_CFG(DIV_APB3, 0) 
                DIV_CFG(DIV_APB4, 0) 
                DIV_CFG(DIV_APBDBG, 0) 
        >; 

        st,kerclk = < 
                MUX_CFG(MUX_D3PER, MUX_D3PER_MSI) 

        >; 

        pll1:st,pll-1 { 
                st,pll = <&pll1_cfg_2176MHz>; 

                pll1_cfg_2176MHz: pll1-cfg-2176MHz{ 
                        cfg = <34 1 1 1>; 
                        src=<MUX_CFG(MUX_MUXSEL5, MUXSEL_HSI)>; 
                }; 
                /* USER CODE BEGIN pll1 */ 
                /* USER CODE END pll1 */ 
        }; 

        pll2:st,pll-2 { 
                st,pll = <&pll2_cfg_600MHz>; 

                pll2_cfg_600MHz: pll2-cfg-600MHz{ 
                        cfg = <37 1 1 4>; 
                        src=<MUX_CFG(MUX_MUXSEL6, MUXSEL_HSI)>; 
                        frac = < 0x800000 >; 
                }; 
                /* USER CODE BEGIN pll2 */ 
                /* USER CODE END pll2 */ 
        }; 

        pll8:st,pll-8 { 
                st,pll = <&pll8_cfg_2176MHz>; 

                pll8_cfg_2176MHz: pll8-cfg-2176MHz{ 
                        cfg = <34 1 1 1>; 
                        src=<MUX_CFG(MUX_MUXSEL4, MUXSEL_HSI)>; 
                }; 
                /* USER CODE BEGIN pll8 */ 
                /* USER CODE END pll8 */ 
        }; 

        /* USER CODE BEGIN rcc */ 
        /* USER CODE END rcc */ 
};

#include "stm32mp25-fw-config.dtsi" 

/ { 
        st-mem-firewall { 
                bl31_context: bl31-context@81fc0000 { 
                        reg = <0x0 0x81fc0000 0x0 0x40000>; 
                        st,protreg = <RISAFPROT(RISAF_REG_ID(7), 0, RIF_UNUSED, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>; 
                }; 
                op_tee: op-tee@82000000 { 
                        reg = <0x0 0x82000000 0x0 0x2000000>; 
                        st,protreg = <RISAFPROT(RISAF_REG_ID(8), 0, RIF_UNUSED, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>; 
                }; 
        }; 
        /* USER CODE BEGIN root */ 
        /* USER CODE END root */ 
};

 * Copyright (C) 2026, STMicroelectronics - All Rights Reserved 
 * Author: STM32CubeMX code generation for STMicroelectronics. 
 */ 

/* For more information on Device Tree configuration, please refer to 
 * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration 
 */ 
#include "stm32mp25-fw-config.dtsi" 

/ { 
        st-mem-firewall { 
                bl31_context: bl31-context@81fc0000 { 
                        reg = <0x0 0x81fc0000 0x0 0x40000>; 
                        st,protreg = <RISAFPROT(RISAF_REG_ID(7), 0, RIF_UNUSED, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>; 
                }; 
                op_tee: op-tee@82000000 { 
                        reg = <0x0 0x82000000 0x0 0x2000000>; 
                        st,protreg = <RISAFPROT(RISAF_REG_ID(8), 0, RIF_UNUSED, RIF_UNUSED, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>; 
                }; 
        }; 
        /* USER CODE BEGIN root */ 
        /* USER CODE END root */ 
};

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer

STM32MP257FAK3 custom board with STM64-OS as operating system: https://github.com/DanielMartensson/STM64-Computer

DMårt · ‎2026-02-09

@PatrickF

Here is a longer output of the error message. I think there is something in the DT that are missing.

NOTICE:  Early console setup
mmap:
 VA:0xe017000  PA:0xe017000  size:0x21000  attr:0x2  granularity:0x40000000
 VA:0xe000000  PA:0xe000000  size:0x40000  attr:0x4a  granularity:0x40000000
 VA:0xe040000  PA:0xe040000  size:0x10000  attr:0x4a  granularity:0x40000000
 VA:0x40000000  PA:0x40000000  size:0x40000000  attr:0x48  granularity:0x40000000

VERBOSE: Translation tables state:
VERBOSE:   Xlat regime:     EL3
VERBOSE:   Max allowed PA:  0x1ffffffff
VERBOSE:   Max allowed VA:  0x1ffffffff
VERBOSE:   Max mapped PA:   0x7fffffff
VERBOSE:   Max mapped VA:   0x7fffffff
VERBOSE:   Initial lookup level: 1
VERBOSE:   Entries @initial lookup level: 8
VERBOSE:   Used 2 sub-tables out of 4 (spare: 2)
  [LV1] VA:0x0 size:0x40000000
    [LV2] VA:0x0 size:0x200000
    [LV2] (111 invalid descriptors omitted)
    [LV2] VA:0xe000000 size:0x200000
      [LV3] VA:0xe000000 PA:0xe000000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe001000 PA:0xe001000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe002000 PA:0xe002000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe003000 PA:0xe003000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe004000 PA:0xe004000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe005000 PA:0xe005000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe006000 PA:0xe006000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe007000 PA:0xe007000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe008000 PA:0xe008000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe009000 PA:0xe009000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe00a000 PA:0xe00a000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe00b000 PA:0xe00b000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe00c000 PA:0xe00c000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe00d000 PA:0xe00d000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe00e000 PA:0xe00e000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe00f000 PA:0xe00f000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe010000 PA:0xe010000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe011000 PA:0xe011000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe012000 PA:0xe012000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe013000 PA:0xe013000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe014000 PA:0xe014000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe015000 PA:0xe015000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe016000 PA:0xe016000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe017000 PA:0xe017000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe018000 PA:0xe018000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe019000 PA:0xe019000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe01a000 PA:0xe01a000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe01b000 PA:0xe01b000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe01c000 PA:0xe01c000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe01d000 PA:0xe01d000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe01e000 PA:0xe01e000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe01f000 PA:0xe01f000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe020000 PA:0xe020000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe021000 PA:0xe021000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe022000 PA:0xe022000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe023000 PA:0xe023000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe024000 PA:0xe024000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe025000 PA:0xe025000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe026000 PA:0xe026000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe027000 PA:0xe027000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe028000 PA:0xe028000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe029000 PA:0xe029000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe02a000 PA:0xe02a000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe02b000 PA:0xe02b000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe02c000 PA:0xe02c000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe02d000 PA:0xe02d000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe02e000 PA:0xe02e000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe02f000 PA:0xe02f000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe030000 PA:0xe030000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe031000 PA:0xe031000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe032000 PA:0xe032000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe033000 PA:0xe033000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe034000 PA:0xe034000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe035000 PA:0xe035000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe036000 PA:0xe036000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe037000 PA:0xe037000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0xe038000 PA:0xe038000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe039000 PA:0xe039000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe03a000 PA:0xe03a000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe03b000 PA:0xe03b000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe03c000 PA:0xe03c000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe03d000 PA:0xe03d000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe03e000 PA:0xe03e000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe03f000 PA:0xe03f000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe040000 PA:0xe040000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe041000 PA:0xe041000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe042000 PA:0xe042000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe043000 PA:0xe043000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe044000 PA:0xe044000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe045000 PA:0xe045000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe046000 PA:0xe046000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe047000 PA:0xe047000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe048000 PA:0xe048000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe049000 PA:0xe049000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe04a000 PA:0xe04a000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe04b000 PA:0xe04b000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe04c000 PA:0xe04c000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe04d000 PA:0xe04d000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe04e000 PA:0xe04e000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe04f000 PA:0xe04f000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0xe050000 size:0x1000
      [LV3] (431 invalid descriptors omitted)
    [LV2] VA:0xe200000 size:0x200000
    [LV2] (398 invalid descriptors omitted)
  [LV1] VA:0x40000000 PA:0x40000000 size:0x40000000 DEV-RW-XN-S
  [LV1] VA:0x80000000 size:0x40000000
  [LV1] (5 invalid descriptors omitted)
VERBOSE: Couldn't find property st,drive in dtb
VERBOSE: Couldn't find property st,drive in dtb
VERBOSE: Couldn't find property st,drive in dtb
VERBOSE: Couldn't find property st,drive in dtb
VERBOSE: Couldn't find property csg in dtb
VERBOSE: Couldn't find property frac in dtb
VERBOSE: Couldn't find property csg in dtb
VERBOSE: Couldn't find property frac in dtb
VERBOSE: Couldn't find property csg in dtb
VERBOSE: Couldn't find property frac in dtb
VERBOSE: Generic delay timer configured with mult=1 and div=64
ERROR:   failed to enable clock id: 5
BACKTRACE: START: clk_stm32_enable_call_ops
0: EL3: 0xe017bac
1: EL3: 0xe01c210
2: EL3: 0xe01c294
3: EL3: 0xe01c338
4: EL3: 0xe01c640
5: EL3: 0xe01df28
6: EL3: 0xe02b118
7: EL3: 0xe0170dc
BACKTRACE: END: clk_stm32_enable_call_ops
PANIC at PC : 0x000000000e01c218

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer

STM32MP257FAK3 custom board with STM64-OS as operating system: https://github.com/DanielMartensson/STM64-Computer

PatrickF · ‎2026-02-09

Hi,

maybe there is some missing DT information expected as mandatory by TF-A

st,drive sound like oscillator like LSE or HSE
csg and frac maybe be related to PLL

Altough not seen in https://github.com/STMicroelectronics/arm-trusted-firmware/blob/v2.10-stm32mp/fdts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi

It might be elsewhere (missing 'include' somewhere ?)

Sorry not helping more. This is out of my knowledge.

Regards.

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DMårt · ‎2026-02-11

@PatrickF

Yes. LSE was ID 5. But I don't know if I'm in need of LSE. I don't have any RTC or tamper activated. I have not even LSE activated at all.

NOTICE:  Early console setup
NOTICE:  clk_stm32_get_oscillator_name: id = 0
NOTICE:  clk_stm32_get_oscillator_name: id = 1
NOTICE:  clk_stm32_get_oscillator_name: id = 2
NOTICE:  clk_stm32_get_oscillator_name: id = 3
NOTICE:  clk_stm32_get_oscillator_name: id = 4
NOTICE:  clk_stm32_get_oscillator_name: id = 5
NOTICE:  clk_stm32_get_oscillator_name: id = 6
NOTICE:  clk_stm32_init: priv->num = 152
NOTICE:  clk_stm32_init: i = 0
NOTICE:  clk_stm32_init: i = 1
NOTICE:  clk_stm32_init: ops->init(priv, 1)
NOTICE:  clk_stm32_osc_init: id = 1, name = clk-hsi
NOTICE:  clk_stm32_init: i = 2
NOTICE:  clk_stm32_init: ops->init(priv, 2)
NOTICE:  clk_stm32_osc_init: id = 2, name = clk-hse
NOTICE:  clk_stm32_init: i = 3
NOTICE:  clk_stm32_init: ops->init(priv, 3)
NOTICE:  clk_stm32_osc_init: id = 3, name = clk-msi
NOTICE:  clk_stm32_init: i = 4
NOTICE:  clk_stm32_init: ops->init(priv, 4)
NOTICE:  clk_stm32_osc_init: id = 4, name = clk-lsi
NOTICE:  clk_stm32_init: i = 5
NOTICE:  clk_stm32_init: ops->init(priv, 5)
NOTICE:  clk_stm32_osc_init: id = 5, name = clk-lse
NOTICE:  clk_stm32_init: i = 6
NOTICE:  clk_stm32_init: ops->init(priv, 6)
NOTICE:  clk_stm32_osc_init: id = 6, name = i2s_ckin
NOTICE:  clk_stm32_init: i = 7
NOTICE:  clk_stm32_init: ops->init(priv, 7)
NOTICE:  clk_stm32_osc_init: id = 7, name = spdif_symb
NOTICE:  clk_stm32_init: i = 8
NOTICE:  clk_stm32_init: i = 9
NOTICE:  clk_stm32_init: i = 10
...
NOTICE:  clk_stm32_init: i = 151
NOTICE:  _clk_stm32_enable: CLK Lock
NOTICE:  _clk_stm32_enable_core: if (parent != CLK_IS_ROOT)
NOTICE:  _clk_stm32_enable_core: Calling clk_stm32_enable_call_ops
NOTICE:  clk_stm32_enable_call_ops: Enabling with id = 2
NOTICE:  _clk_stm32_enable_core: Increase priv->gate_refcounts[2] from 0 to 1
NOTICE:  _clk_stm32_enable: CLK Unlock: 0
NOTICE:  _clk_stm32_enable: CLK Lock
NOTICE:  _clk_stm32_enable_core: if (parent != CLK_IS_ROOT)
NOTICE:  _clk_stm32_enable_core: Calling clk_stm32_enable_call_ops
NOTICE:  clk_stm32_enable_call_ops: Enabling with id = 3
NOTICE:  _clk_stm32_enable_core: Increase priv->gate_refcounts[3] from 0 to 1
NOTICE:  _clk_stm32_enable: CLK Unlock: 0
NOTICE:  _clk_stm32_enable: CLK Lock
NOTICE:  _clk_stm32_enable_core: if (parent != CLK_IS_ROOT)
NOTICE:  _clk_stm32_enable_core: Calling clk_stm32_enable_call_ops
NOTICE:  clk_stm32_enable_call_ops: Enabling with id = 4
NOTICE:  _clk_stm32_enable_core: Increase priv->gate_refcounts[4] from 0 to 1
NOTICE:  _clk_stm32_enable: CLK Unlock: 0
NOTICE:  _clk_stm32_enable: CLK Lock
NOTICE:  _clk_stm32_enable_core: if (parent != CLK_IS_ROOT)
NOTICE:  _clk_stm32_enable_core: Calling clk_stm32_enable_call_ops
NOTICE:  clk_stm32_enable_call_ops: Already enabled with id = 1
NOTICE:  _clk_stm32_enable_core: Increase priv->gate_refcounts[1] from 0 to 1
NOTICE:  _clk_stm32_enable: CLK Unlock: 0
NOTICE:  _clk_stm32_enable: CLK Lock
NOTICE:  _clk_stm32_enable_core: Increase priv->gate_refcounts[2] from 1 to 2
NOTICE:  _clk_stm32_enable: CLK Unlock: 0
NOTICE:  _clk_stm32_enable: CLK Lock
NOTICE:  _clk_stm32_enable_core: Increase priv->gate_refcounts[3] from 1 to 2
NOTICE:  _clk_stm32_enable: CLK Unlock: 0
NOTICE:  _clk_stm32_enable: CLK Lock
NOTICE:  _clk_stm32_enable_core: Increase priv->gate_refcounts[4] from 1 to 2
NOTICE:  _clk_stm32_enable: CLK Unlock: 0
NOTICE:  _clk_stm32_enable: CLK Lock
NOTICE:  _clk_stm32_enable_core: if (parent != CLK_IS_ROOT)
NOTICE:  _clk_stm32_enable_core: Calling clk_stm32_enable_call_ops
NOTICE:  clk_stm32_enable_call_ops: Enabling with id = 5
ERROR:   failed to enable clock id: 5
BACKTRACE: START: clk_stm32_enable_call_ops
0: EL3: 0xe017bac
1: EL3: 0xe01bf04
2: EL3: 0xe01bfb4
3: EL3: 0xe01c060
4: EL3: 0xe01c3ac
5: EL3: 0xe01dd0c
6: EL3: 0xe029c10
7: EL3: 0xe0170dc
BACKTRACE: END: clk_stm32_enable_call_ops
PANIC at PC : 0x000000000e01bf0c

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer

STM32MP257FAK3 custom board with STM64-OS as operating system: https://github.com/DanielMartensson/STM64-Computer

DMårt · ‎2026-02-12

Hi @PatrickF

I just want to say that I made an if-statement that check if the LSE is disabled. If they are disabled, it should only print out a warning and not call the panic function.

I think that the ST's tf-a assumes that both LSE and HSI should be active.

To reproduce this:

1. Remove the LSE crystal from DK/EV board

2. Disable LSE in CubeMX

3. Recompile new OpenSTLinux

4. Boot

5. View the early boot log

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer

STM32MP257FAK3 custom board with STM64-OS as operating system: https://github.com/DanielMartensson/STM64-Computer

OlivierK · ‎2026-04-10

Hello @DMårt

Thank you for your feedback, a patch is now available from OSTL DV6.1.1. It deactivates the external oscillator when not available, and prevents panic. It applies for STM32MP2xx and STM32MP1xx product familes.

For reference: https://community.st.com/t5/stm32-mpus-products-and-hardware/stm32mp135a-needs-an-lse-meta-st-stm32mp/m-p/858884#M15494

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.