DSI panel works in u-boot but not in kernel.

ASoul.1 · ‎2020-12-30

Hello,

I'd like to drive a DSI panel using STM32MP157AAC Rev.Z.

I have no problem with the panel in the u-boot and everything is ok [i can see the u-boot splash screen].

So the hardware on both sides [board and panel] is ok, the panel init sequence, dts config, dsi, ltdc, bridge config and drivers are ok,....

but after kernel start, the panel is not working any more:

1- I can confirm the initial sequence works fine,

2- Even, i can read the internal register of panel in LP mode in kernel boot time.

3- drm, bridge, panel connection to ltdc, cma memory allocation are ok, [i add a lot of debuging print], there is no error from any modules and everything seems ok.

4- I can confirm pll is ok, The pll and clock config is fully similar to u-boot configs.

***But in the DSI video mode, the panel is not showing anything.

[Using oscilloscope]: I can see the lanes signal in DSI video mode of u-boot but after entering DSI videos mode in kernel there is no activity in lanes,

At this point I am confused, Respectfully, please let me know if you have any idea.

Thank you in advanced.

Regards,

Ali

ASoul.1 · ‎2021-01-04

I am writing these for future reference.

I tried to port the TV070WSM-TL0 as a MIPI DSI panel in a custom design board.

this panel is utilized in some tablet like HUAWEI mediapad T1 701u and the driver IC is HX8394-D.

The resolution of the panel is 600x1024, with 4 lanes of data. There is no publicly availed datasheet for HX8394-D.

As I explained before the panel works OK in u-boot but I did not succeed in kernel

To prove all the timings is Ok I enabled the DSI host test pattern generator. Which is explained in “36.11.1 Color bar pattern�? of DSI Host (DSI) of RM0436 Reference manual of STM32MP157.

#ifdef CONFIG_DEBUG_FS
dsi->vpg = 1;
    if (dsi->vpg) {
        val |= VID_MODE_VPG_ENABLE;
        val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
    }
#endif /* CONFIG_DEBUG_FS */

The result is shown in bellow picture:

The panel mode structure is as bellow, [based on TV070WSM-TL0 datasheet].

static const struct drm_display_mode default_mode = {
    .clock = 42400,
    .hdisplay = 600,
    .hsync_start = 600 + 20,
    .hsync_end = 600 + 36 + 24,
    .htotal = 600 + 20 + 36 + 24,
    .vdisplay = 1024,
    .vsync_start = 1024 + 8,
    .vsync_end = 1024 + 6 + 2,
    .vtotal = 1024 + 8 + 6 + 2,
    .vrefresh = 60,
    .flags = 0,
    .width_mm = 89,
    .height_mm = 153,
};

I extracted the initial sequence of the panel from binary file of android boot-loader of the referred tablet. Just I change the number of lanes from 4 to 2 to be in compatible with stm32mp157.

if(my_dcs_write_cmd(ctx, 0xB9, 3,  (u8[]){0xFF,0x83,0x94}) != 0)
        return -1;
    my_dcs_write_cmd(ctx, 0xBA, 0x09, (u8[]){0x61,0x83,0xA0,0x65,0xB2,0x1B,0x1B,0x40,0x10});
    msleep(20);
    my_dcs_write_cmd(ctx, 0xB1, 0x0F, (u8[]){0x6C,0x0E,0x0E,0x25,0x04,0x0F,0xEF,0x01,0x68,0xDA,0x23,0x86,0xC0,0x8A,0x58});
    my_dcs_write_cmd(ctx, 0xB2, 0x0C, (u8[]){0x85,0x44,0x0F,0x09,0x24,0x1C,0x08,0x08,0x1C,0x4D,0x00,0x00});
    my_dcs_write_cmd(ctx, 0xB4, 0x0C, (u8[]){0x00,0xFF,0x84,0x85,0x84,0x85,0x84,0x85,0x01,0x76,0x15,0x76});
    my_dcs_write_cmd(ctx, 0xBF, 0x03, (u8[]){0x41,0x0E,0x01});
    my_dcs_write_cmd(ctx, 0xD2, 0x01, (u8[]){0x00});
    my_dcs_write_cmd(ctx, 0xD3, 0x1E, (u8[]){0x00,0x01,0x00,0x01,0x07,0x0C,0x0C,0x32,0x10,0x07,0x00,0x05,0x00,0x20,0x0A,0x05,0x09,0x00,0x32,0x10,0x08,0x00,0x21,0x21,0x08,0x07,0x23,0x0D,0x07,0x47});
    my_dcs_write_cmd(ctx, 0xD5, 0x2C, (u8[]){0x01,0x00,0x01,0x00,0x03,0x02,0x03,0x02,0x21,0x20,0x21,0x20,0x18,0x02,0x18,0x02,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18});
    my_dcs_write_cmd(ctx, 0xE0, 0x2A, (u8[]){0x00,0x06,0x0C,0x28,0x2D,0x3D,0x1A,0x37,0x07,0x0A,0x0D,0x18,0x0E,0x12,0x15,0x13,0x15,0x06,0x10,0x11,0x16,0x00,0x06,0x0C,0x28,0x2C,0x3D,0x1A,0x37,0x07,0x0A,0x0C,0x18,0x0F,0x12,0x15,0x13,0x14,0x06,0x10,0x11,0x16});
    my_dcs_write_cmd(ctx, 0xBD, 0x01, (u8[]){0x00});
    my_dcs_write_cmd(ctx, 0xC1, 0x2B, (u8[]){0x01,0x00,0x07,0x0F,0x16,0x1E,0x25,0x2E,0x37,0x40,0x49,0x51,0x58,0x60,0x69,0x71,0x7A,0x81,0x89,0x91,0x99,0xA1,0xA9,0xB1,0xB8,0xC1,0xC9,0xD1,0xD9,0xE1,0xE8,0xF0,0xF7,0xFF,0x02,0xB0,0x00,0x00,0x00,0x00,0x00,0x00,0x00});
    my_dcs_write_cmd(ctx, 0xBD, 0x01, (u8[]){0x01});
    my_dcs_write_cmd(ctx, 0xC1, 0x2A, (u8[]){0x00,0x07,0x0F,0x16,0x1E,0x25,0x2E,0x37,0x40,0x49,0x51,0x59,0x61,0x69,0x71,0x79,0x81,0x88,0x90,0x98,0x9F,0xA7,0xAF,0xB7,0xBE,0xC6,0xCE,0xD7,0xDD,0xE4,0xEB,0xF2,0xF8,0x3F,0x95,0x52,0xE4,0x1D,0x17,0x00,0xA5,0x00});
    my_dcs_write_cmd(ctx, 0xBD, 0x01, (u8[]){0x02});
    my_dcs_write_cmd(ctx, 0xC1, 0x2A, (u8[]){0x00,0x05,0x0C,0x13,0x1A,0x22,0x2A,0x32,0x3B,0x43,0x4B,0x52,0x5A,0x61,0x68,0x70,0x78,0x7F,0x85,0x8D,0x94,0x9B,0xA2,0xA9,0xB0,0xB7,0xBE,0xC6,0xCE,0xD5,0xDB,0xE2,0xE8,0x76,0x9F,0xCA,0x60,0x30,0x94,0x02,0x78,0x00});
    my_dcs_write_cmd(ctx, 0xCC, 0x01, (u8[]){0x09});
    my_dcs_write_cmd(ctx, 0xC7, 0x04, (u8[]){0x00,0xC0,0x00,0xC0});
    my_dcs_write_cmd(ctx, 0xC0, 0x02, (u8[]){0x30,0x14});
    my_dcs_write_cmd(ctx, 0xBC, 0x01, (u8[]){0x07});
    my_dcs_write_cmd(ctx, 0x35, 0x01, (u8[]){0x00});//TE mode
    my_dcs_write_cmd(ctx, 0x11, 0x00, (u8[]){});
    msleep(120);
    my_dcs_write_cmd(ctx, 0xC6, 0x02, (u8[]){0x3D,0x00});
    msleep(5);
    my_dcs_write_cmd(ctx, 0x29, 0x00, (u8[]){});
    msleep(20);
    my_dcs_write_cmd(ctx, 0x55, 0x01, (u8[]){0x01});
    msleep(20);
    my_dcs_write_cmd(ctx, 0xE4, 0x02, (u8[]){0xD3,0x00});
    msleep(10);
    my_dcs_write_cmd(ctx, 0xE5, 0x2B, (u8[]){0x00,0x0F,0x10,0x10,0x10,0x0A,0x05,0x05,0x05,0x05,0x50,0x1A,0x0A,0x00,0x03,0x10,0x0E,0x0E,0x20,0x08,0x09,0x0A,0x0E,0x0B,0x0B,0x0A,0x0A,0x09,0x06,0x05,0x03,0x0D,0x14,0x01,0x0F,0x00,0x1C,0x12,0x03,0x0B,0x1A,0x14,0x05});
    msleep(10);
    my_dcs_write_cmd(ctx, 0xE6, 0x11, (u8[]){0x00,0x00,0x00,0x05,0x05,0x08,0x08,0x08,0x0C,0x0C,0x0C,0x08,0x08,0x08,0x08,0x08,0x08});
    msleep(50);

I tested the lower refresh rate, with RGB888 and RGB565 and …. Which all works in u-boot, but not in kernel.

To show the bridge, connector, ltdc, dsi, .. configuration is Ok i show the result of modetest:

# modetest -M stm
Encoders:
id      crtc    type    possible crtcs  possible clones
31      35      DSI     0x00000001      0x00000000
 
Connectors:
id      encoder status          name            size (mm)       modes   encoders
32      31      connected       DSI-1           89x153          1       31
  modes:
        name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
  600x1024 50 600 620 660 680 1024 1032 1032 1040 42400 flags: ; type: preferred, driver

------------------------------------------------------------------------------------

# modetest -M stm -s 32@35:600x1024 -v
setting mode 600x1024-50Hz@XR24 on connectors 32, crtc 35
freq: 56.38Hz
freq: 55.99Hz
freq: 56.00Hz
freq: 55.99Hz
freq: 55.99Hz

P.S: And finally i did not figure out why the St provided such irregular and nested driver for DSI, dw-mipi-dsi.c <-> dw_mipi_dsi-stm.c.

Regards,

Ali

Mariano Abad · ‎2021-01-13

Did you make some progress with the panel?