DP83867 bring up issues - STM32MP131

[devinschubert14]

Hi everyone,

I am trying to bring up the DP83867 with RGMII on the STM32MP131DAG7. However I am getting the following error:

[   18.253959] stm32-dwmac 5800a000.ethernet end0: renamed from eth0
[   23.695184] stm32-dwmac 5800a000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
[   23.756147] stm32-dwmac 5800a000.ethernet end0: PHY [stmmac-0:00] driver [TI DP83867] (irq=POLL)
[   24.764629] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[   24.769435] stm32-dwmac 5800a000.ethernet end0: stmmac_hw_setup: DMA engine initialization failed
[   24.808705] stm32-dwmac 5800a000.ethernet end0: __stmmac_open: Hw setup failed

I saw this is typically due to the 125MHz clock not being generated. In our schematic, we have the CLK_OUT from phy going to ETH_RGMII_CLK125. I noticed the phy was not generating a clock so using the "mii" tool in U-Boot, I tried to generate the clock by updating the 0x0170 register: Link I was unable to get any clock to generate even though the 25MHz clock was generated by crystal, all power rails were up, MDIO was communicating correctly, GTX_CLK was at 125MHz, and reset pin was not active (it seems driver never even tries to reset it). I gave up on this method and moved on to generating internally with RCC.

I updated the TF-A and OPTEE dts to generate the 125MHz clock as seen here:

root@stm32mp131-sga:~# cat /sys/kernel/debug/clk/clk_summary
pll3_q                              1       1        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
    ck_ker_eth1                      1       1        0        125000000   0          0     50000      Y      deviceless                      no_connection_id
       eth1ptp_k                     0       0        0        125000000   0          0     50000      Y         deviceless                      no_connection_id
       eth1ck_k                      1       1        0        125000000   0          0     50000      Y         5800a000.ethernet               eth-ck

Updated the u-boot and kernel dts: (adding st, ext-phyclk)

eth1_rgmii_pins_mx: eth1-rgmii-mx-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
                                 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
                                 <STM32_PINMUX('C', 2, AF11)>,  /* ETH_RGMII_TXD2 */
                                 <STM32_PINMUX('E', 5, AF10)>,  /* ETH_RGMII_TXD3 */
                                 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_EN */
                                 <STM32_PINMUX('C', 1, AF11)>,  /* ETH_RGMII_GTX_CLK */
                                 //<STM32_PINMUX('F', 12, AF11)>, /* ETH_RGMII_CLK125 */
                                 <STM32_PINMUX('G', 12, AF11)>, /* ETH_PHY_INTN */
                                 <STM32_PINMUX('G', 2, AF11)>;  /* ETH_MDC */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <2>;
                };

                pins2 {
                        pinmux = <STM32_PINMUX('G', 3, AF11)>; /* ETH_MDIO */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <0>;
                };

                pins3 {
                        pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
                                 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
                                 <STM32_PINMUX('B', 0, AF11)>, /* ETH1_RXD2 */
                                 <STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
                                 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
                        bias-disable;
                };
        };

        eth1_sleep_pins_mx: eth1_sleep_mx-0 {
                pins {
                        pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
                                         <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_TXD1 */
                                         <STM32_PINMUX('C', 2, ANALOG)>,  /* ETH_RGMII_TXD2 */
                                         <STM32_PINMUX('E', 5, ANALOG)>,  /* ETH_RGMII_TXD3 */
                                         <STM32_PINMUX('G', 2, ANALOG)>, /* ETH1_MDC */
                                         <STM32_PINMUX('G', 3, ANALOG)>, /* ETH1_MDIO */
                                         <STM32_PINMUX('G', 12, ANALOG)>, /* ETH_PHY_INTN */
                                         <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_RGMII_RX_CTL */
                                         <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
                                         <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
                                         <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
                                         <STM32_PINMUX('B', 0, ANALOG)>, /* ETH1_RXD2 */
                                         <STM32_PINMUX('B', 1, ANALOG)>, /* ETH1_RXD3 */
                                         <STM32_PINMUX('A', 11, ANALOG)>;  /* ETH_RGMII_CLK */
                };
        };

&ethernet1 {
        status = "okay";
        pinctrl-0 = <&eth1_rgmii_pins_mx>;
        pinctrl-1 = <&eth1_sleep_pins_mx>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii-id";
        max-speed = <1000>;
        phy-handle = <&phy0_eth1>;
        phy-supply = <&scmi_vdd_system>;
        nvmem-cells = <&ethernet_mac1_address>;
        nvmem-cell-names = "mac-address";
        st,ext-phyclk;

        mdio {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0_eth1: ethernet-phy@0 {
                compatible = "ethernet-phy-id2000.a231";
                reg = <0>;
                reset-gpios = <&gpiod 5 GPIO_ACTIVE_LOW >;
                interrupt-parent = <&gpiog>;
                interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
                ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
             };
        };
};

 Using both methods I still get the same error message as above. I also tried different options for ti,clk-output-sel and the ti,tx/rx-internal-delay and commenting out reset gpios, but no difference.

In summary:

1. Tried to generate clock from phy, unable to do so

2. Generated 125MHz clock internally, same error message as before

Any guidance would be greatly appreciated as I feel I have tried every configuration.