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DP83867 bring up issues - STM32MP131

devinschubert14
Associate III

‎2025-09-29 12:28 PM - edited ‎2025-09-29 12:34 PM

Hi everyone,

 

I am trying to bring up the DP83867 with RGMII on the STM32MP131DAG7. However I am getting the following error:

[   18.253959] stm32-dwmac 5800a000.ethernet end0: renamed from eth0
[   23.695184] stm32-dwmac 5800a000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
[   23.756147] stm32-dwmac 5800a000.ethernet end0: PHY [stmmac-0:00] driver [TI DP83867] (irq=POLL)
[   24.764629] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[   24.769435] stm32-dwmac 5800a000.ethernet end0: stmmac_hw_setup: DMA engine initialization failed
[   24.808705] stm32-dwmac 5800a000.ethernet end0: __stmmac_open: Hw setup failed

 

I saw this is typically due to the 125MHz clock not being generated. In our schematic, we have the CLK_OUT from phy going to ETH_RGMII_CLK125. I noticed the phy was not generating a clock so using the "mii" tool in U-Boot, I tried to generate the clock by updating the 0x0170 register: Link I was unable to get any clock to generate even though the 25MHz clock was generated by crystal, all power rails were up, MDIO was communicating correctly, GTX_CLK was at 125MHz, and reset pin was not active (it seems driver never even tries to reset it). I gave up on this method and moved on to generating internally with RCC.

 

I updated the TF-A and OPTEE dts to generate the 125MHz clock as seen here:

root@stm32mp131-sga:~# cat /sys/kernel/debug/clk/clk_summary
pll3_q                              1       1        0        125000000   0          0     50000      Y   deviceless                      no_connection_id
    ck_ker_eth1                      1       1        0        125000000   0          0     50000      Y      deviceless                      no_connection_id
       eth1ptp_k                     0       0        0        125000000   0          0     50000      Y         deviceless                      no_connection_id
       eth1ck_k                      1       1        0        125000000   0          0     50000      Y         5800a000.ethernet               eth-ck

Updated the u-boot and kernel dts: (adding st, ext-phyclk)

eth1_rgmii_pins_mx: eth1-rgmii-mx-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
                                 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
                                 <STM32_PINMUX('C', 2, AF11)>,  /* ETH_RGMII_TXD2 */
                                 <STM32_PINMUX('E', 5, AF10)>,  /* ETH_RGMII_TXD3 */
                                 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_EN */
                                 <STM32_PINMUX('C', 1, AF11)>,  /* ETH_RGMII_GTX_CLK */
                                 //<STM32_PINMUX('F', 12, AF11)>, /* ETH_RGMII_CLK125 */
                                 <STM32_PINMUX('G', 12, AF11)>, /* ETH_PHY_INTN */
                                 <STM32_PINMUX('G', 2, AF11)>;  /* ETH_MDC */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <2>;
                };

                pins2 {
                        pinmux = <STM32_PINMUX('G', 3, AF11)>; /* ETH_MDIO */
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <0>;
                };

                pins3 {
                        pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
                                 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
                                 <STM32_PINMUX('B', 0, AF11)>, /* ETH1_RXD2 */
                                 <STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
                                 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
                        bias-disable;
                };
        };

        eth1_sleep_pins_mx: eth1_sleep_mx-0 {
                pins {
                        pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
                                         <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_TXD1 */
                                         <STM32_PINMUX('C', 2, ANALOG)>,  /* ETH_RGMII_TXD2 */
                                         <STM32_PINMUX('E', 5, ANALOG)>,  /* ETH_RGMII_TXD3 */
                                         <STM32_PINMUX('G', 2, ANALOG)>, /* ETH1_MDC */
                                         <STM32_PINMUX('G', 3, ANALOG)>, /* ETH1_MDIO */
                                         <STM32_PINMUX('G', 12, ANALOG)>, /* ETH_PHY_INTN */
                                         <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_RGMII_RX_CTL */
                                         <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
                                         <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
                                         <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
                                         <STM32_PINMUX('B', 0, ANALOG)>, /* ETH1_RXD2 */
                                         <STM32_PINMUX('B', 1, ANALOG)>, /* ETH1_RXD3 */
                                         <STM32_PINMUX('A', 11, ANALOG)>;  /* ETH_RGMII_CLK */
                };
        };

 

&ethernet1 {
        status = "okay";
        pinctrl-0 = <&eth1_rgmii_pins_mx>;
        pinctrl-1 = <&eth1_sleep_pins_mx>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii-id";
        max-speed = <1000>;
        phy-handle = <&phy0_eth1>;
        phy-supply = <&scmi_vdd_system>;
        nvmem-cells = <&ethernet_mac1_address>;
        nvmem-cell-names = "mac-address";
        st,ext-phyclk;

        mdio {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0_eth1: ethernet-phy@0 {
                compatible = "ethernet-phy-id2000.a231";
                reg = <0>;
                reset-gpios = <&gpiod 5 GPIO_ACTIVE_LOW >;
                interrupt-parent = <&gpiog>;
                interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
                ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
             };
        };
};

 Using both methods I still get the same error message as above. I also tried different options for ti,clk-output-sel and the ti,tx/rx-internal-delay and commenting out reset gpios, but no difference.

 

In summary:

1. Tried to generate clock from phy, unable to do so

2. Generated 125MHz clock internally, same error message as before

 

Any guidance would be greatly appreciated as I feel I have tried every configuration.

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6 REPLIES 6
Erwan SZYMANSKI
ST Employee

‎2025-10-06 12:24 AM

Hello @devinschubert14 ,
Do you have some schematics you are able to share ? At least the part between the SoC connections and the PHY ?
I see you tried a lot of different method and properties, but I think the best way is to focus on one goal you want to reach and investigate in this sense.

If you tried to generate the 125MHz from the outside (the PHY), I guess you have a 25MHz crystal in your design. You should so at probe time, see at one moment that this 125MHz clock comes in input of the SoC (ETHX_CLK125 pin).

Then you should check that ETH1_CLK_SEL value is well at 0 (Gates are manipulated by properties in device tree). The clock tree is documented in the RM (see below an extract):

 

ErwanSZYMANSKI_0-1759735297495.png

Do not hesitate to check too at this wiki article that can help: https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration

Kind regards,
Erwan.

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devinschubert14
Associate III
In response to Erwan SZYMANSKI

‎2025-10-06 11:33 AM - edited ‎2025-10-06 11:34 AM

Hi Erwan,

 

We originally tried to have the phy generate the 125MHz clock for the ETH1_RGMII_CLK125 pin, so let's keep trying in this direction.

 

I have followed the wiki article very closely. I do not have 125MHz clock coming from the PHY. I have looked with an oscope and there is no activity, however the 25MHz crystal is working. It seems the dp83867 driver never configures the 0x0170 register so it will never get the clock.

This setting is configured with:

ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;

I tried to use MDIO in u-boot to tell the phy to generate the clock by updating the 0x0170 register: Link I can see the register value is being updated, but the clock is still not generated.

I am aware of the ETH1_CLK_SEL which is set by the: st, ext-phyclk. If we are discussing having the phy generate the clock, this parameter should be removed from ethernet1 node in .dts.

 

I have done a ton of debugging so I am trying not to give too many details but I have tried many things.

 

Here is schematic:
SoC:

devinschubert14_1-1759774600289.png

 

Phy:

devinschubert14_2-1759774648284.png

 

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Erwan SZYMANSKI
ST Employee
In response to devinschubert14

‎2025-10-07 2:04 AM - edited ‎2025-10-07 2:19 AM

Hello @devinschubert14 ,
I begin to review the information you gave above. I just begin but I already see that the interruption described in the DTS under mdio node looks wrong isn't it ? 

According to your schematics, it seems that the interrupt is coming on PG12 but the device tree mentions PG11. PG11 looks like an unconnected pin.

[Edit: I see you declared it in pinctrl directly, but I do not understand so what is this interrupt declared in mdio node]

Kind regards,
Erwan.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
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Erwan SZYMANSKI
ST Employee
In response to Erwan SZYMANSKI

‎2025-10-07 4:33 AM

@devinschubert14 ,
I took a look at your pinctrl and compared with your schematics, OK for most of pins but I am surprised. I do not see the ETH_RGMII_RXCLK. It should come on PA1 according to your schematics and is mandatory to get a correct setup.

Kind regards,
Erwan.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
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devinschubert14
Associate III
In response to Erwan SZYMANSKI

‎2025-10-07 11:48 AM

Hi Erwan,

 

I think this is just remnant from me debugging, I have removed it from the ethernet node.

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devinschubert14
Associate III
In response to Erwan SZYMANSKI

‎2025-10-07 11:54 AM - edited ‎2025-10-07 11:59 AM

@Erwan SZYMANSKI 

Good catch! That was definitely a mistake on my part.

I have made the change to the dts and it seems I am getting the same error. I noticed the phy still was not generating a 125MHz signal so I tried generating the clock internally and same error message.

 

I did notice that after the driver fails the reset pin is driven low and stays there, I do not know if this could be part of the issue?

 

Updated Pinctrl:

eth1_rgmii_pins_mx: eth1-rgmii-mx-0 {
		pins1 {
			pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
				 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
                 <STM32_PINMUX('C', 2, AF11)>,  /* ETH_RGMII_TXD2 */
				 <STM32_PINMUX('E', 5, AF10)>,  /* ETH_RGMII_TXD3 */
				 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_EN */
				 <STM32_PINMUX('C', 1, AF11)>,  /* ETH_RGMII_GTX_CLK */
				 //<STM32_PINMUX('F', 12, AF11)>, /* ETH_RGMII_CLK125 */
				 <STM32_PINMUX('G', 12, AF11)>, /* ETH_PHY_INTN */
				 <STM32_PINMUX('G', 2, AF11)>;  /* ETH_MDC */
			bias-disable;
			drive-push-pull;
			slew-rate = <2>;
		};
		
		pins2 {
			pinmux = <STM32_PINMUX('G', 3, AF11)>; /* ETH_MDIO */
			bias-disable;
			drive-push-pull;
			slew-rate = <0>;
		};

		pins3 {
			pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
                     <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
                     <STM32_PINMUX('B', 0, AF11)>, /* ETH1_RXD2 */
                     <STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
                     <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RGMII_RX_CLK */
                     <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
			bias-disable;
		};
	};
	
	eth1_sleep_pins_mx: eth1_sleep_mx-0 {
		pins {
			pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
					 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_TXD1 */
                     <STM32_PINMUX('C', 2, ANALOG)>,  /* ETH_RGMII_TXD2 */
                     <STM32_PINMUX('E', 5, ANALOG)>,  /* ETH_RGMII_TXD3 */
					 <STM32_PINMUX('G', 2, ANALOG)>, /* ETH1_MDC */
                     <STM32_PINMUX('G', 3, ANALOG)>, /* ETH1_MDIO */
                     <STM32_PINMUX('G', 12, ANALOG)>, /* ETH_PHY_INTN */
                     <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RGMII_RX_CLK */
					 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_RGMII_RX_CTL */
					 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */

 

Edit: After removing gpio from ethernet1 node, the reset pin remained high but still same error message

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