STM32MP157F DDR Caching/Organization

[heelsec]

Hello, we are currently working with the STM32MP157F-DK2 evaluation board. We have a couple questions regarding the DDR setup on the board. First, when accessing DDR memory, is there any level of CPU caching occurring, or can the memory region have cache disabled? For example, on ARMv7, memory regions can be mapped with certain attributes to ensure requests are always served from memory. It seems like only some STM32 board models have L1 caching, and this board is not one of them. We want to ensure that when we access a DDR memory location, the request is being served to the memory controller.

Also, we are a bit confused by the organization for the DDR addressing. We use 32-bit addresses, which are then converted to the appropriate row/column/bank numbers in DDR. We are currently running the default firmware listed on the "Getting Started with M4" guide. We are consulting the DDRCTRL registers and the Reference Manual for the board. The DDRCTRL_MSTR register bits 13, 12 (DATA_BUS_WIDTH) bits have value 01, meaning Half Bus Width (each memory address holds 16 bits.) DDRCTRL_ADDRMAP1 has value 0x70707, meanings address bits 11-9 map to bank bits 2-0 (4, 3, 2 all + 7 internal value). DDRCTRL_ADDRMAP2 has value 0x0, meaning address bits 5-2 map to column bits 6-3. DDRCTRL_ADDRMAP3 has value 0x1F000000, meaning address bits 8-6 map to column bits 9-7 and column bit 10 is unused. DDRCTRL_ADDRMAP5 has value 0x60606, meaning address bits 23-12 map to row bits 11-0. DDRCTRL_ADDRMAP6 has value 0xF060606, meaning address bits 26-24 map to row bits 14-12.

So, given a 32-bit address, the current mapping is as shown:

The board is listed as 4-Gbit of DDR3L, 16-bit width of each column. So, we need (4 * 1024 * 1024 * 1024) / (16) columns, or (256 * 1024 * 1024). If we have 8 banks (2^3 bits), and 2^15 rows, then we need (256 * 1024 * 1024) / (8 * 2^15) columns, or 1024 columns. This makes sense, but we only have 7 bits for picking the column, when we need 10. Even if address bits 1 and 0 are for picking the column and not specified in a DDRCTRL register, we still need one more bit to pick the column in this case. Am I wrong about the size of the column width, or am I reading the registers incorrectly?

Thank you in advance.