Hello,
We are using the LBEE5KL1DX-883 WLAN+BT chip with a STM32MP157C on a custom board. The SDIO interface is routed to the SDMMC3 interface (different from the DK-2 board). However when we are probing the brcmfmac module, it cannot find the mmc0 interface it seems. It writes the following to the dmesg logs:
[ 21.319324] brcmfmac: No platform data available.
Is there anything extra which needs to be configured when using SDMMC3 as opposed to SDMMC2? Posting relevant configuration below. Thanks
mmc related dmesg logs during boot:
root@stm32mp1:~# dmesg | grep mmc
[ 0.000000] Kernel command line: root=/dev/mmcblk1p5 rootwait rw console=ttySTM0,115200
[ 1.799815] mmci-pl18x 48004000.sdmmc: allocated mmc-pwrseq
[ 1.804262] mmci-pl18x 48004000.sdmmc: Linked as a consumer to regulator.7
[ 1.810928] mmci-pl18x 48004000.sdmmc: mmc0: PL180 manf 53 rev1 at 0x48004000 irq 41,0 (pio)
[ 1.848186] mmci-pl18x 58005000.sdmmc: Linked as a consumer to regulator.7
[ 1.853931] mmci-pl18x 58005000.sdmmc: mmc1: PL180 manf 53 rev2 at 0x58005000 irq 48,0 (pio)
[ 2.005479] mmc1: host does not support reading read-only switch, assuming write-enable
[ 2.020796] mmc1: new high speed SDHC card at address aaaa
[ 2.038625] mmcblk1: mmc1:aaaa SC32G 29.7 GiB
[ 2.162810] mmcblk1: p1 p2 p3 p4 p5 p6
/sys/kernel/debug/mmc0/ios
root@stm32mp1:/sys/kernel/debug/mmc0# cat ios
clock: 0 Hz
vdd: 0 (invalid)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 0 (off)
bus width: 0 (1 bits)
timing spec: 0 (legacy)
signal voltage: 0 (3.30 V)
driver type: 0 (driver type B)
Kernel SDMMC3 DT entry:
/* Wifi */
&sdmmc3 {
arm,primecell-periphid = <0x10153180>;
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_b4_pins_a>;
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
non-removable;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
keep-power-in-suspend;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
U-Boot clock setup:
st,pkcs = <
CLK_CKPER_HSE
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_DISABLED
CLK_SPI2S23_PLL3Q
CLK_SPI45_PCLK2
CLK_SPI6_DISABLED
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_DISABLED
CLK_CEC_DISABLED
CLK_I2C12_DISABLED
CLK_I2C35_DISABLED
CLK_UART1_DISABLED
CLK_UART24_PCLK1
CLK_UART35_PCLK1
CLK_UART6_DISABLED
CLK_UART78_PCLK1
CLK_SPDIF_DISABLED
CLK_FDCAN_HSE
CLK_SAI1_DISABLED
CLK_SAI2_DISABLED
CLK_SAI3_DISABLED
CLK_SAI4_DISABLED
CLK_RNG1_LSI
CLK_LPTIM1_DISABLED
CLK_LPTIM23_DISABLED
CLK_LPTIM45_DISABLED
>;
