Introduction
Clock configuration is a fundamental aspect of microcontroller (MCU) design, directly influencing the performance and power consumption of the system. In the STM32 series, the reset and clock control (RCC) peripheral manages the system clock, providing multiple sources and configurations to suit various application needs. This article delves into the intricacies of clock dividers and multipliers using the STM32H5 series as an example. We explore how different configurations can achieve the same system clock (SYSCLK) frequency and discuss the implications of these configurations.
1. Clock sources in the STM32H5
Generally, you can find information about clock sources in the datasheet, in the electrical characteristics paragraph or in the clock tree of your product's reference manual:
- High-Speed External (HSE) Clock: An accurate external oscillator with frequencies ranging from 4 MHz to 50 MHz
- High-Speed Internal (HSI) Clock: A 64 MHz internal RC oscillator, less accurate than HSE but with a faster startup time
- Low-Speed External (LSE) Clock: A 32.768 kHz external oscillator, typically used for real-time clock (RTC) applications
- Low-Speed Internal (LSI) Clock: A 32 kHz internal RC oscillator, used for low-power operations
- Clock Security System (CSI): A 4 MHz internal RC oscillator, balancing power consumption and startup time
- HSI48: A 48 MHz RC oscillator, primarily used for USB and RNG peripherals
2. Practical example
In this example, we try to achieve a SYSCLK of 120 MHz using different configurations.
Starting from the STM32CubeMX clock configuration:
Configuration 1: CSI (4 MHz) → Divider (/4) → Multiplier (x240) → Divider (/2) → SYSCLK = 120 MHz
Configuration 2: CSI (4 MHz) → Divider (/1) → Multiplier (x60) → Divider (/2) → SYSCLK = 120 MHz
Configuration 3: CSI (4 MHz) → Divider (/2) → Multiplier (x240) → Divider (/4) → SYSCLK = 120 MHz
All above configurations yield the same SYSCLK frequency, but their performance and power consumption may differ.
3. Evaluating configurations
3.1 Jitter and stability
The primary consideration when choosing a configuration is the jitter and stability of the PLL. Higher multiplication factors can introduce more jitter, which is detrimental to the performance of analog peripherals like ADCs and DACs.
Configuration 2, with a lower multiplication factor (x60), is likely to have better jitter performance compared to other configurations (x240).
From the STM32H563 datasheet, table 48. "PLL characteristics (wide VCO frequency range)" the cycle-to-cycle jitter is as follows:
Using higher multipliers in the PLL configuration can lead to increased cycle to cycle jitter, this is because the VCO runs for a longer period.
3.2 Power consumption
Power consumption is another critical factor. Higher frequencies in the PLL stages can lead to increased power consumption, as follows:
Conclusion
The choice of PLL configuration involves balancing the need for low jitter against the low-power consumption. For applications requiring high precision and stable clock signals, higher VCO frequencies with lower jitter are preferable, despite the higher power consumption.
