Introduction
This article provides answers to frequently asked questions regarding Parallel Synchronous Slave Interface (PSSI) and includes a list of useful resource links.
1. Frequently asked questions about PSSI
1.1 Can PSSI transmit or receive data without connecting PSSI_PDCK to a clock source
No. Transmitting and receiving data require the PSSI_PDCK clock. Without a clock connected to the PSSI_PDCK, it is impossible to send or receive any data bits.
Note that the PSSI_PDCK can be generated by an RCC (for example,MCO2) or by an external clock source (for example, a timer) connected to the PSSI_PDCK pin.
1.2 How to configure PSSI_PDCK
When configuring the PSSI_PDCK clock, ensure that the AHB clock frequency is at least 2.5 times higher than the PSSI_PDCK frequency, because the PSSI is mapped to AHB. This ratio is critical for proper operation. At frequency ratios lower than 2.5, data might be corrupted or lost during transfers.
1.3 Known limitations
The following STM32 devices have a known limitation:
- STM32L4P5xx and STM32LQ5xx
- STM32U5
- STM32H7A3/7B3, STM32H7B0, STM32H723/733, STM32H725/735, STM32H730, and STM32H7Rx/7Sx
- STM32N6x5/x7xx
- STM32H523/33xx, STM32H562/63xx, STM32H573xx, STM32H5E4/5F4, and STM32H5E5/5F5
Issue: Output mode not usable with both PSSI_RDY and PSSI_DE signals enabled
Description: In output mode, when both the PSSI_RDY and PSSI_DE signals are enabled (DERDYCFG[2:0] bitfield set to 011,100, or 111), the PSSI_DE signal may fail to indicate data validity.
As a result, output mode cannot be used when both PSSI_RDY and PSSI_DE signals are enabled.
Workaround: None.
2. Useful links for PSSI
