Integrating and debugging external memory on STM32 MCUs: part 1 – hardware and device fundamentals

EBowdach · ‎2025-12-22

Summary

This article addresses the critical process of integrating and debugging external memory on STM32 microcontrollers, emphasizing a systematic approach that integrates hardware verification, firmware configuration, and validation. It highlights the importance of understanding memory device specifications, ensuring signal integrity, and correctly initializing peripherals. In part 2, we highlight key firmware settings, middleware usage, and debugging strategies to ensure robust and reliable external memory operation in real-world applications.

Summary
Introduction
Overview
1. Understanding your memory device
1.1 Start with the memory datasheet
1.2 Industry standards
2. Hardware-level debugging checklist
2.1 Pin mapping and schematic
2.2 Power and decoupling
2.3 Pull-ups/pull-downs and termination
2.4 Clocking
2.5 Reset and boot
2.6 PCB layout
Conclusion
Related links

Introduction

As ST expands its portfolio with more flash-less MCUs, external memory becomes essential for expanding storage and execution space beyond internal flash and RAM limits. This enables larger applications, data logging, and faster access through memory-mapped interfaces. However, integration challenges require a structured debugging approach covering hardware verification, firmware configuration, and validation. This guide walks you through these key steps to ensure reliable external memory operation.

Overview

The integration and debugging process for external memory can be organized into these essential stages:

Understanding your memory device
Hardware-level verification
Firmware configuration and initialization
Debugging and validation

In part 1 of this series, we focus on the first two steps: understanding your memory device and performing hardware-level verification. The remaining steps are covered in part 2.

1. Understanding your memory device

1.1 Start with the memory datasheet

Every memory device has unique characteristics: timings, command sets, power-up sequences, and operational modes. For example, some memories enter standby mode by default, requiring specific commands to wake them. Pay particular attention to:

Power-up and reset sequences
Required mode or bus width selection
Timing parameters (setup, hold, refresh rates)
Signal requirements (pull-ups, termination)

This foundational knowledge guides all subsequent steps. These steps are applicable to different types of external memory, including SDRAM, SRAM, NOR/NAND Flash, PSRAM, eMMC, and more.

1.2 Industry standards

Industry standards are essential when integrating external memory with STM32 MCUs, ensuring interoperability and simplifying design. They define common interfaces and protocols, enabling confident selection from various vendors. Leveraging these standards allows developers to use robust middleware and reference designs, making integration more reliable and future-proof. Below are some key industry standards that exist today:

JEDEC SFDP (Serial Flash Discoverable Parameters):

Standard for NOR flash devices.
Allows MCUs to automatically detect memory features and supported commands for seamless integration.

ONFI (Open NAND Flash Interface):

Common protocol for NAND flash devices.
Defines command sets, timing, and parameter pages for interoperability across vendors.

JEDEC SDRAM/PSRAM standards:

Specifies initialization sequences, timing, and electrical characteristics for SDRAM and PSRAM.
Ensures compatibility with memory controllers like STM32’s FMC.

SPI, QSPI, OPI, and HyperBus protocols:

Standardized serial interfaces for high-speed RAM and flash (e.g., SPI, quad-SPI, Octa SPI, HyperBus).
Enable efficient communication with MCUs equipped with matching peripherals.

Selecting external memories that comply with these standards ensures broad compatibility, easier debugging, and access to proven software and hardware resources. As an example, here is a link and a snippet from the MX25U25645G datasheet, a 1.8 V, 256M-BIT CMOS NOR Serial Flash Memory, of the memory’s Read SFDP Mode. This memory is similar to the memory used on the NUCLEO-H7S3L8 board, MX25UW25645G. The MX25U25645G memory device complies with JEDEC standards for Serial Flash Discoverable Parameters (SFDP), which provide a standardized method to describe memory characteristics and timings.

2. Hardware-level debugging checklist

When debugging external memory, it’s easy to focus on firmware, but hardware checks are often crucial. Even the best software can’t fix issues like missing pull-ups, swapped lines, or noisy clocks. High-speed memory interfaces are sensitive to signal integrity, power stability, and correct pin mapping. A single hardware oversight, such as a floating chip select or poor power filtering, can cause subtle or total failures hard to detect in software. Starting with hardware ensures a solid foundation, as hardware and software must both be correct for reliable operation. There are many ways to connect external memory to an STM32:

PSSI (Parallel Synchronous Slave Interface)
FMC (Flexible Memory Controller)
SPI (QSPI, XSPI, etc.)
I2C

Although these vary in their connection and data transfer methods, similar approaches can be used to verify their correct connection to the STM32. Keep the MCU datasheet, reference manual, and hardware design guide (AN5935: Getting started with STM32H7Rx/7sx MCUs hardware development) on hand alongside the memory device datasheet.

2.1 Pin mapping and schematic

Double-check all data, address, control, and clock lines are correctly routed between MCU and memory.
Verify alternate function (AF) settings for each pin in the MCU datasheet and STM32CubeMX.
Confirm that all required signals are connected (for example, CS, SCLK, DQ0 – DQn, RESET, VCC, GND).

2.2 Power and decoupling

Ensure that all memory and MCU supply pins are powered at the correct voltages.
Place adequate decoupling capacitors close to memory and MCU VDD/VSS pins.
Check for proper VREF/VREFQ if required by the memory type.

2.3 Pull-ups/pull-downs and termination

Add pull-ups on CS, RESET, and other control lines as recommended by the memory datasheet. This prevents these signals from floating during programming, which can cause spurious operations or bus contention.
For high-speed interfaces (XSPI, SDRAM), consider series resistors for signal integrity.

2.4 Clocking

Verify that the memory clock is present, at the correct frequency, and stable.
For QSPI/XSPI, check that the clock polarity and phase match the memory’s requirements.

2.5 Reset and boot

Ensure that the memory device is properly reset and out of reset before access.
Check for correct strapping pins (for example, for address, mode, or bus width selection).

2.6 PCB layout

Keep high-speed traces short, matched in length, and routed with controlled impedance.
Avoid stubs, sharp corners, and crossing split ground planes.
Separate analog and digital grounds.
AN5935 has more details on PCB layout guidelines for high speed signal layouts for SDMMC, FMC, XSPI in section 10.4 (for the STM32H7R/S), please see XSPI details from section 10.4.3 below:

Conclusion

In this first part, we have covered the foundational aspects of integrating and debugging external memory on STM32 MCUs, focusing on understanding memory device specifications and performing thorough hardware-level verification. These steps are crucial to establishing a reliable hardware foundation and ensuring compatibility with STM32 peripherals. In part 2, we continue by exploring firmware configuration and initialization, followed by debugging and validation techniques to help you confidently troubleshoot and optimize your external memory integration. Click here to read part 2.