Can an SDRAM memory be executed below its clock memory?

[ARodr.16]

I was looking at the 32F469IDISCOVERY board schematic, because I am developing a board with a TFT-LCD screen, and I was looking at the schematic as a reference to connect an SDRAM. But one thing caught my attention, and that is that the data bus of the memory indicates that the frequency is 90 MHz, that makes sense if we look at the maximum HCLK clock of the MCU is 180MHz so with a speed of HCLK/2 gives us that value.

Now, looking at the datasheet of the ISSI_IS42S32400F-6BL SDRAM memory, I noticed that the memory frequency is 166 MHz or 100 Mhz if the lowest latency is used.How is it possible that SDRAM memory can operate below this value? Does this imply that you can choose any SDRAM memory and run it below its minimum clock value or is this characteristic of this memory?

[Tesla DeLorean]

Yes you can use derated speeds, timed measurement in cycles, round up cycles to be at least as long as minimums

[ARodr.16]

so as long as you respect the minimum times and cycles, you can run at any frequency you want? there is no limit?