At the debug mode I would not like to provide .elf file , as the generated elf file does not have CRC that is generated .
In STM system workbench I use post build command to generate .bin file and than I use srec-cat script to generate CRC on this .bin file at end of post build process I get .bin+CRC from my project.
at this point I want to load into the controller file generated post build .bin+CRC file , and not .elf file as elf file does not have the CRC for the file content in it.
Can we load .bin file in place of .elf file for debug purposes in the system workbench for stm32 , I do not need break points , I know I can load the same file using j_flash utility but I want this process with system workbench
