2017-01-16 11:44 AM
Solved! Go to Solution.
2017-01-16 11:51 AM
As it turns out, the problem was the setting for OC4M in TIM4->CCMR2. Verified that modes 0000 and 0001 do not work and mode 0110 does work. I had mistakenly thought that mode 0001 would set OC4REF high for one timer clock, while CNT is equal to the compare value, and low otherwise. Apparently it's actually a latching behavior, which doesn't generate an edge every cycle, and the ADC EXTEN is documented as looking for edges. The PWM mode reliably generates edges.
Also, CC4E in CCER must be set.
From these observations, I conclude that the signal which reaches the ADC hardware trigger block is the one labelled 'OC4' on the Timers block diagram.
Unlike the other posts linked above, I do not need to map this signal all the way to an output pin in order to see the ADC trigger. Perhaps one of the CMSIS functions used in that code had multiple effects, such as configuring the timer output enables at the same time as mapping the pin function. Using the register interface there is no such issue.
2017-01-16 11:51 AM
As it turns out, the problem was the setting for OC4M in TIM4->CCMR2. Verified that modes 0000 and 0001 do not work and mode 0110 does work. I had mistakenly thought that mode 0001 would set OC4REF high for one timer clock, while CNT is equal to the compare value, and low otherwise. Apparently it's actually a latching behavior, which doesn't generate an edge every cycle, and the ADC EXTEN is documented as looking for edges. The PWM mode reliably generates edges.
Also, CC4E in CCER must be set.
From these observations, I conclude that the signal which reaches the ADC hardware trigger block is the one labelled 'OC4' on the Timers block diagram.
Unlike the other posts linked above, I do not need to map this signal all the way to an output pin in order to see the ADC trigger. Perhaps one of the CMSIS functions used in that code had multiple effects, such as configuring the timer output enables at the same time as mapping the pin function. Using the register interface there is no such issue.