2025-08-13 2:39 AM
Dear all,
I’m seeing unexpected behavior on an STM32N657. A timer is configured to generate an interrupt every 1 ms, and this works as expected.
I would like to use WFI to stop execution and wait for that timer interrupt. I surround the WFI with the usual barriers (DSB before, ISB after). However, when I use WFI, the timer no longer synchronizes and the interrupt is never taken. With WFE, the system resumes correctly, but that is not the functionality I need.
The same code works on my other ST targets (M3, M4, M7, M33), and it also works on a non-ST Cortex-M55. I haven’t found anything relevant in the errata.
Could you please advise or point me to any known issues or configuration requirements related to WFI on the STM32N657?
Many thanks in advance.
Kind regards,
Edo
Solved! Go to Solution.
2025-08-25 12:36 AM
Dear all,
Issue resolved.
Root cause:
When the CPU executes WFI, peripheral clocks are gated, so a timer cannot tick and therefore cannot generate an interrupt to wake the core.
Fix:
Enable the timer clock and its low-power clock in the RCC so the timer keeps running during WFI.
Tested on our side with TIM5:
RCC->APB1LENR |= RCC_APB1LENR_TIM5EN; // Enable TIM5 clock
RCC->APB1LLPENR |= RCC_APB1LLPENR_TIM5LPEN; // Keep TIM5 clock enabled in low-power
With this in place, TIM5 continues counting and can assert its interrupt, which wakes the CPU from WFI as expected.
Best regards,
Edo
2025-08-25 12:36 AM
Dear all,
Issue resolved.
Root cause:
When the CPU executes WFI, peripheral clocks are gated, so a timer cannot tick and therefore cannot generate an interrupt to wake the core.
Fix:
Enable the timer clock and its low-power clock in the RCC so the timer keeps running during WFI.
Tested on our side with TIM5:
RCC->APB1LENR |= RCC_APB1LENR_TIM5EN; // Enable TIM5 clock
RCC->APB1LLPENR |= RCC_APB1LLPENR_TIM5LPEN; // Keep TIM5 clock enabled in low-power
With this in place, TIM5 continues counting and can assert its interrupt, which wakes the CPU from WFI as expected.
Best regards,
Edo