Tim 3 Clock Frequency Understanding

[blue_dolphin1987]

Posted on February 26, 2014 at 07:03

Hi i am referring to an example from the stm32f4 library.

In the comment section :

TIM3 Configuration: Output Compare Toggle Mode:
In this example TIM3 input clock (TIM3CLK) is set to 2 * APB1 clock (PCLK1), 
since APB1 prescaler is different from 1. 
TIM3CLK = 2 * PCLK1 
PCLK1 = HCLK / 4 
=> TIM3CLK = HCLK / 2 = SystemCoreClock /2

My question is why is TIM3CLK = 2 * PLK1 shouldnt it be TIM3CLK = APB1 = HCLK /4 ? And what does it mean by

TIM3 input clock (TIM3CLK) is set to 2 * APB1 clock (PCLK1)

Isnt TIM3 input clock by default APB1 ? Thanks.

[waclawek.jan]

Posted on February 26, 2014 at 09:38

RM0090 rev.6, ch.7.2, p.213:

The timer clock frequencies are automatically set by hardware. There are two cases:

1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected. They might've mentioned it in the timers' chapters, though... JW