Synchronized (Chained/Cascaded) Timers

Question

Posted on June 06, 2012 at 18:13Newbie here...I'd like to use one timer as a prescaler for another. Both these timers (combined) will act like a single 48-bit ''uptime'' value, used for timestamping events. The master timer will be driven off APBx.I have found a ton of info about how to use the timers in complex scenarios, but I couldn't find sufficient information for my (quite simple) needs. I'm familiar with both the STM32F417 Reference Manual and the STM32F4xx Timer Overview documents.First question: can someone explain the TIMx_SMCR.MSM bit? A timing diagram (with and without) would be a nice addition to the Reference Manual.We've had race condition problems on our previous platform where, e.g., the ''subsecond'' counter would roll over before the ''second'' counter; I'm guessing MSM has something to do with preventing this condition. But it also mentions it ''delays'' the TRGI; we're planning on running these timers extremely fast, but we can't miss a pulse.So, if someone could explain the exact semantics of MSM, that would be great.Thanks!       -Steve #stm32f417-timer-synchronized

Tesla DeLorean · Answer

Posted on June 06, 2012 at 19:47How fast exactly? I personally wouldn't bother with using the timers in this mode for timestamping, reading them atomically will just be a pig. I'd used the core's cycle counter that exists within the trace unit, this will run at 168 MHz, I'd use perhaps 24 or 30 bits of that for precision, and then use a SysTick based check to see if it had rolled over within my truncated precision limits, ie look at high order bits.http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337g/BABJFFGJ.html#BABHBDAH For the ethernet parts you might look to see if the 64-bit IEEE-1588 timestamp registers are usable.

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