SVC_Handler fails badly - hardfaults

Posted on September 06, 2013 at 19:27

What's the value in LR when it fails? I'd imagine it's a magic value indicating which stack was used? 0xFF??????

The stack push/pop aren't balanced.

Posted on September 06, 2013 at 23:41

Is the stack aligned to a word boundary?

  Jack Peacock

Posted on September 09, 2013 at 09:17

>What's the value in LR when it fails? I'd imagine it's a magic value indicating which >stack was used? 0xFF??????

Yes, the magic.

>The stack push/pop aren't balanced.

Yes, i see, copied wrong.  But thats not the problem (at that moment)

Posted on September 09, 2013 at 10:00

Sorry i just correct a little my original post,  _but__ this is just because I was doing 4 things at same time, the copying to forum went wrong.

name SVC_Handler

public SVC_Handler

section READONLY:CODE

SVC_Handler

 STMFD        sp!,{r0-r3,r12,lr}   ; Store registers.

LDR          r0,[lr, #-4]         ; Calculate address of SWI instruction and load it into r0.

BIC          r0,r0,#0xff000000    ; Mask off top 8 bits of instruction to give SWI number.

; Use value in r0 to determine which SWI routine to execute.

;

  LDMFD        sp!, {r0-r3,r12,pc}^        ; Restore registers and return.

END

I'm puzzled with the instruction .

LDR    r0,[lr, #-4] ; ; and yes its -4 for ARM not Thumb

As clive1 pointed out, lr in when in SVC contains a magic value, the magic

contained in only last 4 bits i think (saw in manual, can't recall page now..)

So how is the above suppose to calculate the address of the SWI instruction

and load it, that's magic to me. But i don't do ARM asm programming :\

May be this does not apply to CortexM3 at all? I have not found a more

CM3 specialized example..

By the way,

LDMFD   sp!, {r0-r3,r12,pc}^

The ^ is 'kinda' important as i read, yet my asm compiler - IAR Systems -

does not accept it..

Posted on September 09, 2013 at 10:03

>Is the stack aligned to a word boundary?

>  Jack Peacock

Jack, now I do this right at start in my hal init:

SCB->CCR |= SCB_CCR_STKALIGN;

Still that SVC of mine promptly hard faults at same place ...

Posted on September 09, 2013 at 11:37

clive1, and the magic in LR is

0xFFFFFFF9.

STM32F10xxx prog manual, p40: EXC_RETURN[3:0] = 0x09 = 0b1001.

 =

''Return to Thread mode.

Exception return gets state from MSP.

Execution uses MSP after return.''

Do you know how that LDR instruction is suppose to do what the comment says it should ..?   Don't know if it explains the hardfault either ...

Posted on September 09, 2013 at 14:29

Yea that's it... Pretty much same as my HardFault_Handler I copied else where, urghhg..

Thanks

Posted on September 09, 2013 at 14:43

void SVC_Handler(void)

{

  __asm volatile(

    ''TST LR, #4      \n''

    ''ITE EQ          \n''

    ''MRSEQ R0, MSP   \n''

    ''MRSNE R0, PSP   \n''

    ''B svc_handler_c''

  );

}

void svc_handler_c (unsigned int * svc_args)

{ 

// ...

 svc_number = ((char *)svc_args[6])[-2];

// ....

}

thanks for pointed to that doc...

Posted on September 29, 2015 at 22:40

Newer, link, will also attach

https://www.arm.com/files/pdf/Cortex-M3_programming_for_ARM7_developers.pdf

________________

Attachments :

Cortex-M3_programming_for_ARM7_developers.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I0f1&d=%2Fa%2F0X0000000bc3%2FRUGmYAkA401NmoX7ETYz1My.x4kbylFjjhjQK6RNYOk&asPdf=false