2012-11-30 12:26 PM
In the M3 Cortex processor world how do I suspend and resume servicing a pending timer interrupt request? In the 8051 world, when the timer overflow the interrupt request flag(TF) is set. If I don't want the timer interrupt service routine to run at the time the request comes in , I would clear the ET flag to stop the interrupt service routine from lanching. Then later when I set the ET flag, the interrupt servie routine would lauch to service the interrupt request (TF). In the Cortex world, what is the equivalent of TF and ET flag. If I clear UIE flag in TIMx_DIER then I will never get a interrupt request. Would it works if set the UIE flag and set the UDIS flag in TIMx_CR1 to suspend the interrupt service routine from lauching? When I clear the UDIS flag would the interrupt service routine launch to service the interrupt request?
Thanks in advance for your help
Ton #i2012-11-30 02:01 PM
Not sure I fully understand the context here, but wouldn't
TIM_ITConfig(TIM3, TIM_IT_Update, DISABLE); TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE); Mask and unmask the interrupt enable without changing the pending state?2012-12-03 06:53 AM
TIM_ITConfig(TIM3, TIM_IT_Update, DISABLE) would stop the generation of any pending interrupt. I have found out using
TIM_UpdateDisableConfig(TIM3, ENABLE); TIM_UpdateDisableConfig(TIM3, DISABLE); would do the trick. It is just not well explained in the Cortex Reference Manual the way it is for the 8051 processor. I don't see the interrupt pending flag specified in any TIMx or NVIC register.