Posted on July 24, 2015 at 17:22Zero wait state still takes 1 cycle, at least in the F4 instruction path the prefetch on a cache hit occurs within the current cycle, instead of one cycle away in some other memory. At that point the flash is actually faster than even tightly coupled memory.
You could look at the flash line width, and cache construction, but I'm not sure it's going to materially improve your assembly optimization beyond trying to keeping the hit rate high, and things aligned within the flash/cache. In all cases you're going to learn more by profiling/benchmarking your code, and quantifying if there is or isn't any speed/current advantage here, vs running with the cache, or from RAM, etc
You could try your local rep for documentation, or app notes, but I tend to think this is one of those trade-secret areas where sufficiently exact mechanics aren't divulged for competitive reasons.
