I am currently struggling to figure out if my current requirents are even possible.
I am building a network controller to controll laser projectors via analog lines.
For that I have an DAC8552 connected to SPI1 and a DAC1240S85 connected to SPI2.
The way I control SPI1 & SPI2 is almost identical so I will focus on SPI1 for now.
I have the following requirements:
- 200k times per second (200kHz) I need 3 bytes being transferred via SPI
- right before and during that transfer an LDAC line needs to be asserted low and afterwards it needs to be brought back up. This is important for the DAC to actually latch the bits
- The timing is critical and must be precise and each transfer must happen within its 5uS timeframe including the LDAC assertion and deassertion.
- I can't have any CPU involvement besides feeding some sort of DMA a new buffer as I also handle Ethernet with LwIP, decoding the network packages and have to do the same with 4 packages later on on SPI2.
My favorite idea so far is to use a timer like TIM3 and generate a PWM signal to produce an LDAC signal on one channel and then trigger an SPI transaction on CH2.
But it really doesn't seem like there is a way to do that.
Since the LDAC line and the SPI clock must be pretty syncronized when an SPI-Byte is being transferred I don't se a way where I can simply keep my SPI being feed with dummy-data by DMA.
I am getting that desperate that I'm actually trying to see if I can exploit the SPI running dry and spoonfeeding it by triggering DMA transfers into it's TX-Fifo.
But would that even work?
There must be a way to properly time and automatically trigger SPI transactions on STM32H7 or am I completely missing the point?
If an answer needs more information or more precise requirements I'm fast to answer
