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STM32F7 code samples for SPI and DCMI in DMA Circular mode with small reward

megahercas6
Senior
Posted on August 20, 2015 at 09:19

 

 

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5 REPLIES 5
stm322399
Senior
Posted on August 21, 2015 at 16:39

Do you have an issue with SPI only ? If yes, put DCMI aside and try to solve your issue with SPI only.

Do you told us that the sofware is ok on F4, but the (more or less) same software fails on F7 ? There are DMA involved ? If so, consider a possible cache issue. Try to disable cache on F7.

megahercas6
Senior
Posted on September 25, 2015 at 11:40

Wow, this is mest up. If some one will ask to make this code for SPL, i would do in minutes, and no one can do it , even if reward is present ? Nice !

jpeacock
Associate III
Posted on September 25, 2015 at 14:05

Consider it a lesson in free market capitalism rather than ''messed up''.  This is a forum to share knowledge in the hope of saving the ''next guy'' struggling with the same problem someone else has solved.  It's called entrepenurial skill in Economics 101, you have to know how to advertise in the right location.

And offering a few surplus parts to pay for the programming is obviously well below market rate for professional embedded engineers.

  Jack Peacock

megahercas6
Senior
Posted on November 09, 2015 at 17:11

Ok, so this is my third wave to get into STM32F7, since i have project where tons of complex math needs to be executed in very short time, so i must use STM32F7.

As long as i go as far away from DMA as i can, i guess i can make it work. But reading article about STM32F7 i found interesting information:

/* Buffers use fro DMA access must begin on an address aligned with the
* D-Cache line and must be an even multiple of the D-Cache line size.
* These size/alignment requirements are necessary so that D-Cache flush
* and invalidate operations will not have any additional effects.
*
* The TX and RX descriptors are normally 16 bytes in size but could be
* 32 bytes in size if the enhanced descriptor format is used (it is not).
*/
/* DMA buffers. DMA buffers must:
*
* 1. Be a multiple of the D-Cache line size. This requirement is assured
* by the definition of RXDMA buffer size above.
* 2. Be aligned a D-Cache line boundaries, and
* 3. Be positioned in DMA-able memory (*NOT* DTCM memory). This must
* be managed by logic in the linker script file.
*
* These DMA buffers are defined sequentially here to best assure optimal
* packing of the buffers.
*/
/* Descriptor allocations */
static union stm32_rxdesc_u g_rxtable[RXTABLE_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
static union stm32_txdesc_u g_txtable[TXTABLE_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
/* Buffer allocations */
static uint8_t g_rxbuffer[RXBUFFER_ALLOC]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
static uint8_t g_txbuffer[TXBUFFER_ALLOC]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));

So maybe thats why i get data, but data was corrupted. who knows
stm322399
Senior
Posted on November 09, 2015 at 18:19

It is more than interesting, it is the basics of dealing with DMA and caches.

When DMA-able data and ordinary data share the same cache line, disaster can happen, hence the recommendation to align buffers. Aligned buffers leave no room for other variables to be allocated on the same cache line.