STM32F4 DMABMR

[loic boillot]

Posted on July 02, 2018 at 17:02

Hello

We work on STM32F407 with the stack LwIP in order to do webserver.

We have work in a first time and we have no problem to di webserver.

Actually, we work on our board, with the same program and we have this problem :

In the function 'ETH_GetSoftwareResetStatus', the bit SR is always to 1.

     FlagStatus ETH_GetSoftwareResetStatus(void)

     {       FlagStatus bitstatus = RESET;       if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)       {         bitstatus = SET;        }        else        {          bitstatus = RESET;        }        return bitstatus;     }

Someone can help me in order to know why this problem exist and how do not have this problem.

Thanks very much .

Loic

[Tesla DeLorean]

Posted on July 02, 2018 at 18:09

>>Someone can help me in order to know why this problem exist and how do not have this problem.

Watch all the clocks and pin configurations, CubeMX hides stuff all over the place, and order of execution isn't always obvious. Check BSP/MSP stuff.

[loic boillot]

Posted on July 03, 2018 at 09:26

Hello

Thanks for your response.

I do not use CubeMx.

We use a phy KSZ8014TL the only difference between the stm32F4 discovery board and our board.

I have compared the pins and the clocks and i do not see any difference.

/******************************************************************************/

/******************************************************************************//******************************************************************************/My GPIOs initialisation is  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC, ENABLE);  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);    SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);

/* Ethernet pins configuration ************************************************/

        ETH_MDIO        --------------> PA2        ETH_MDC       ---------------> PC1        ETH_RMII_REF_CLK-------> PA1        ETH_RMII_CRS_DV -------> PA7        ETH_MII_RX_ER      -------> PB10        ETH_RMII_RXD0      -------> PC4        ETH_RMII_RXD1      -------> PC5        ETH_RMII_TX_EN    -------> PB11        ETH_RMII_TXD0      -------> PB12        ETH_RMII_TXD1      -------> PB13        ETH_RST_PIN         -------> PE2

  /* Configure PA1,PA2 and PA7 */

  GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;  GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL ;  GPIO_Init(GPIOA, &GPIO_InitStructure);  GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);  GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);  GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);

  /* Configure PB10,PB11,PB12 and PB13 */

  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;  GPIO_Init(GPIOB, &GPIO_InitStructure);  GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_ETH);      GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);  GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);  GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);

  /* Configure PC1, PC4 and PC5 */

  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;  GPIO_Init(GPIOC, &GPIO_InitStructure);  GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);  GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);  GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);

  /* Configure the PHY RST  pin */

  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;  GPIO_Init(GPIOE, &GPIO_InitStructure);

  GPIO_ResetBits(GPIOE, GPIO_Pin_2);    

  for (i = 0; i < 20000; i++);  GPIO_SetBits(GPIOE, GPIO_Pin_2);  for (i = 0; i < 20000; i++);

/******************************************************************************/

/******************************************************************************//******************************************************************************/the function ETH_MACDMA_Config:ETH_InitTypeDef ETH_InitStructure;RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);ETH_DeInit();ETH_SoftwareReset();

/* Wait for software reset */

while (ETH_GetSoftwareResetStatus() == SET);

An other idea ?

Thanks.

[Lecordier.Guy]

Posted on July 03, 2018 at 13:19

Did you update the registers in stm32f4xx_hal_conf.h for the Micrel

#if

(0)

/* For DP83848 */

#define

PHY_SR ((uint16_t)0x10)

/*!< PHY status register Offset */

#define

PHY_LINK_STATUS ((uint16_t)0x0001)

/*!< PHY Link mask */

#define

PHY_SPEED_STATUS ((uint16_t)0x0002)

/*!< PHY Speed mask */

#define

PHY_DUPLEX_STATUS ((uint16_t)0x0004)

/*!< PHY Duplex mask */

#else

/* For Micrel KSZ8051RNLi */

#define

PHY_SR ((uint16_t)0x1E)

/*!< PHY status register Offset */

#define

PHY_LINK_STATUS ((uint16_t)0x0100)

/*!< PHY Link mask */

#define

PHY_SPEED_STATUS ((uint16_t)0x0001)

/*!< PHY Speed mask */

#define

PHY_DUPLEX_STATUS ((uint16_t)0x0004)

/*!< PHY Duplex mask */

#endif

Regards

[loic boillot]

Posted on July 09, 2018 at 08:21

Thanks all for your response.

I found the problem : it was a hardware bug on my board : there was no 50MHz with a quartz.

Subject closed.