STM32F2 APB2Periph Clock failure?

[truonggiangmt]

Posted on June 13, 2012 at 17:12

Hello everyone, I'm working on STM32F207VE Kit .

Has anyone ever set the frequency to exceed the limit for APB2 (greater than 60 Mhz).Yesterday, I had set up freqency for APB2 is 120Mhz (by my mistake). To day, the peripherals such as USART1, ADC not work.Now, even the demo program ''USART printf'' in STM32F2xx_StdPeriph_Examples'' package not running, but still good before. And the periphery of ABP1 still function normally!Was APB2 dead?, Is there any explicitly  way to test ABP2 clock source! Thank you!

[Tesla DeLorean]

Posted on June 13, 2012 at 17:29

Was APB2 dead?, Is there any explicitly  way to test ABP2 clock source! 

Not sure you can break the silicon, the higher clock will typically just violate the timing windows (setup/hold/propagation), and things won't work correctly. Just running the chip off HSI (ie no PLL) should be sufficient to test internal peripherals. You could route some internal clocks via the MCO pins. The APB1/APB2 clocks could be exposed in divided down forms via the TIM units attached to each bus.