STM32 interrupt priority

Easily confused?

Some of the registers are a bit file, others a byte file, the exact scope of specific silicon depends on the number of interrupts in the table.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/BHCFCFDB.html

Recognize there are Interrupts and there are System Handlers, the NVIC deals with the former, the Vector table contains both.

>>I'm using assembly language not C language.

Ok, but that shouldn't render you incapable of looking how the CMSIS code exposes/controls the access to the NVIC, and then applying it to the assembler code.

ISER Bit Vector 0xE000E100

ICER Bit Vector 0xE000E180

ISPR Bit Vector 0xE000E200

IPR Byte Vector 0xE000E400

TIM3 would be BIT 29, BYTE INDEX 29, right?

The NVIC base is 0xE000E100

/**
 \ingroup CMSIS_core_register
 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
 \brief Type definitions for the NVIC Registers
 @{
 */
 
/**
 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct
{
 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
 uint32_t RESERVED0[24U];
 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
 uint32_t RSERVED1[24U];
 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
 uint32_t RESERVED2[24U];
 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
 uint32_t RESERVED3[24U];
 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
 uint32_t RESERVED4[56U];
 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
 uint32_t RESERVED5[644U];
 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
 
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
 
/*@} end of group CMSIS_NVIC */

Vector Table entry address VTOR + 0x40 + (29 * 4) -> 0x080000B4

A big thank you for your patience