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STM32 built-in flash endurance test, targeting STM32L4R7.

Msee
Associate

Good day.

Lately, I had carried out a STM32 built-in flash endurance test, targeting STM32L4R7.

I selected a sector which is :

Bank 2, 0x081F F000 - 0x081F FFFF, 4K, page 255

to perform erase and program, with the hope that it could eventually fail. So that we can record a maximum successful erase/program.

After each round of erase/program, there will be a flash read to check if the flash retains correct data, such.

For erase, we compare all bytes are 0xFF

For program, we compare all bytes are “0x01, 0x02 … �? ascending numbers.

  

However, I had perform nearly 600k operations of erase/program, that selected sector is not failing yet, as no data corruption detected yet so far.

This makes me puzzled, as STM32L4R7 datasheet suggests 10K cycles, such:

 

Endurance TA = –40 to +105 °C 10 kcycles

Thus, I’d like to check, what does it mean with 10k cycles in spec, and what would we expect after exceeding this value?

Which will happen first - data corruption or duration of the retention?

As I wonder, the impact of exceeding maximum flash operation is noticeable immediately or not.

BR,

Mike

1 REPLY 1
TDK
Guru

> ...to perform erase and program, with the hope that it could eventually fail. So that we can record a maximum successful erase/program.

Even if you get this chip to fail, there is no guarantee that the next chip will behave in the same way.

Estimating when failure will occur is a much harder problem than ensuring it will work within some finite read/write cycle lifetime. The datasheet specifies minimum 10k, so your chip is meeting the specification.

I would expect performance at ambient (where you're likely testing) to exceed that at elevated temperatures.

> what does it mean with 10k cycles in spec, and what would we expect after exceeding this value?

This means 10,000 temperature cycles from -40 to +105 and back to -40. After you exceed that, the performance is no longer guaranteed, but it will likely still work, similar to how read/write performance is behaving.

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