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przemoo9621
przemoo9621
Associate
August 22, 2016
Question

SCCB, STM32F429DISCO + OV9650

  • August 22, 2016
  • 2 replies
  • 1207 views
Posted on August 22, 2016 at 14:15

Hi,

My code is the same as this post:

/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a//my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/SCCB%20emulation%20by%20I2C%20communication%20problem&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=99

I have a problem with I2C (SCCB) communication. More precisely, when i try to send slave write adress (0x60 - from 0v9650 datasheet), I get ''DONT_CARE_BIT'' = FALSE. It's like ACK, so after this ADDR flag in I2C_SR1 is set..

BUT.. When i go to line:

while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))

and don't do this yet the ADDR flag is reset and it gets stuck because ADDR flag isn't set.

What can be the reason of reset ADDR?

screen from logic analyzer:

0690X00000605LsQAI.png

#i2c #sccb
This topic has been closed for replies.

2 replies

Walid FTITI_O
Walid FTITI_O
Visitor II
August 22, 2016
Posted on August 22, 2016 at 18:42

Hi przemoo9621,

Each device has two addresses. The bits 7 to 1 are defined by the device, bit 0 is defined by the access type. For a write access bit 0 is 0, for a read access, it is one. Thus it depends on the following action what address you actually need.

The 1-bit left shifted address of 0x60is 0xC0

So try to change the

I2C_OwnAddress1

from 0x60 to 0xC0.

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a//my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/I2C2%20hangs%20at%20%20%20while%28%21I2C_CheckEvent%28LSM_I2C%2c%20I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED%29%29%3b&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=6788

For further explanation of previous suggestion follow this

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a//my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/I2C2%20hangs%20at%20%20%20while%28%21I2C_CheckEvent%28LSM_I2C%2c%20I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED%29%29%3b&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=6788

Also, check the voltage input connection of the OV9650 to ensure that the device respond to commands.

-Hannibal-

przemoo9621
przemoo9621Author
Associate
August 22, 2016
Posted on August 22, 2016 at 22:07

Thank you for your reply Hannibal.

I know I2C and SCCB build.

In OV9650 datasheet is written:

''The device slave addresses are 60 for write and 61 for read.''

 

So I suppose that this ''1'' is 8-bit (''read'' bit).

I have set OwnAddress1 on 0xC0 and this fill OAR1 register correct. (look screen)

In STM32F4 RM is written that ADDR flag is set after ACK and this is reset only when:

- after SR2 and SR1 register

- or when PE=0

In my case neither of these options doesn't occur. This flag is just SET after send 7-bit address and RESET before i check this in while loop.

I'm still looking reason why ADDR flag is reset.

0690X00000605RQQAY.png
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