port uclinux on stm32f7?

[sheng yang]

Posted on April 14, 2018 at 15:23

I add earlyprintl support for stm32f767igt,and it seems success.i modified the start_kernel() function as below

extern void printascii(const char *);

asmlinkage __visible void __init start_kernel(void){ char *command_line; char *after_dashes; printascii('iysheng debug!!!!'); }

i get the console output

iysheng debug!!!![ 0.000000] Booting Linux on physical CPU 0x0

[ 0.000000] Linux version 4.4.0-uc0-g17edafa-dirty (shengyang@red.redzone) (gcc version 5.4.0 (GCC) ) #64 PREEMPT Sat Apr 14 20:21:44 CST 2018[ 0.000000] CPU: ARMv7-M [411fc270] revision 0 (ARMv7M), cr=00000000[ 0.000000] CPU: unknown data cache, unknown instruction cache[ 0.000000] Machine model: STMicroelectronics STM32429i-EVAL board[ 0.000000] bootconsole [earlycon0] enabled[ 0.000000] debug: i.....

But when i debug  timer function,i add one line code in file uClinux/linux/drivers/clocksource/timer-stm32.c as

static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)

{ struct stm32_clock_event_ddata *data = dev_id;

writel_relaxed(0, data->base + TIM_SR);

data->evtdev.event_handler(&data->evtdev);

printk('iysheng *******\n'); return IRQ_HANDLED;}

then i get nothing from console,i get confuzed,why could this happen,clk and timer will init after these code i add in start_kernl().So why that happed ,why could i get nothing from the console? 

[stm322399]

Posted on April 15, 2018 at 13:10

My better advice for you is to go for a newer kernel first. 4.4.0 is more than two year old, and STM32 port had a lot of improvement since.

IMHO, the easiest way to go is to try buildroot, carefully avoiding binutils >=2.29

[sheng yang]

Posted on April 18, 2018 at 18:53

 ,

 ,

thanks for your advice,i use a dsb code here to solve this bug,code in arch/arm/mm/proc-v7m.S.

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S

 ,

old mode 100755

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new mode 100644

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index b390d32..67d9209

 ,

--- a/arch/arm/mm/proc-v7m.S

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+++ b/arch/arm/mm/proc-v7m.S

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@@ -81,12 +81,11 @@ ENDPROC(cpu_v7m_do_resume)

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* This should be able to cover all ARMv7-M cores.

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*/

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__v7m_setup:

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-

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@ Configure the vector table base address

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ldr r0, =BASEADDR_V7M_SCB

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ldr r12, =vector_table

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str r12, [r0, V7M_SCB_VTOR]

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-

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+

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@ enable UsageFault, BusFault and MemManage fault.

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ldr r5, [r0, ♯ V7M_SCB_SHCSR]

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orr r5, ♯ (V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)

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@@ -105,25 +104,22 @@ __v7m_setup:

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mov r6, lr @ save LR

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mov r7, sp @ save SP

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ldr sp, =__v7m_setup_stack_top

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- dsb @ ensure data Synchronization Barrier <,

mailto:iysheng@163.com

>,

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- cpsie i @ enable interrupt

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+ cpsie i

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svc ♯ 0

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-

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-1: cpsid i @disable interrupt

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-

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+1: cpsid i

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str r5, [r12, ♯ 11 * 4] @ restore the original SVC vector entry

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mov lr, r6 @ restore LR

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mov sp, r7 @ restore SP

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-

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+

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@ Special-purpose control register

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mov r1, ♯ 1

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msr control, r1 @ Thread mode has unpriviledged access

 ,

 ,

- @ Configure the System Control Register to ensure 8-byte stack alignment

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+ @ Configure the System Control Register to ensure 8-byte stack alignment

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@ Note the STKALIGN bit is either RW or RAO.

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- @ ldr r12, [r0, V7M_SCB_CCR] @ system control register

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- @ orr r12, ♯ V7M_SCB_CCR_STKALIGN @ bit 9 of V7M_SCB_CCR if read only

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- @ str r12, [r0, V7M_SCB_CCR]

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+ ldr r12, [r0, V7M_SCB_CCR] @ system control register

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+ orr r12, ♯ V7M_SCB_CCR_STKALIGN

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+ str r12, [r0, V7M_SCB_CCR]

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ret lr

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ENDPROC(__v7m_setup)

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