Porblem with IS66WVH64M8DBLL-166B1LI and STM32H723VGT6

[DMast.1]

Good morning,

I'm writing because we are spending a lot of time in the last weeks due experiencing a problem accessing the 64MByte external RAM (IS66WVH64M8DBLL-166B1LI) via Hyperbus on our target board. If we replace the ISSI memory with a Cypress/Infineon, we can access the memory in bytes, words, or dwords with no problem. To exclude layout issues on our board, we purchased the STM32H735G-DK evb and, after verifying that everything worked correctly with the original memory, we replaced it with the 64MByte ISSI and the same problems we're having with our board appear. Specifically, accessing bytes at even addresses results in no errors, while trying to write and re-read bytes at odd addresses results in significant errors. The situation doen's change even if we let's slow down with clock (20MHz). 

Here is the device init code

/* Initialize OctoSPI ----------------------------------------------------- */
OSPIHandle.Instance = OCTOSPI2;
HAL_OSPI_DeInit(&OSPIHandle);

OSPIHandle.Init.FifoThreshold = 4;
OSPIHandle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
OSPIHandle.Init.MemoryType = HAL_OSPI_MEMTYPE_HYPERBUS;

OSPIHandle.Init.DeviceSize = POSITION_VAL(OSPI_RAM_SIZE);

OSPIHandle.Init.ChipSelectHighTime = 4;//>> 2;
OSPIHandle.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
OSPIHandle.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0;
OSPIHandle.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED;
OSPIHandle.Init.ClockPrescaler = 2;//>> 4;
OSPIHandle.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE;
OSPIHandle.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;//>> HAL_OSPI_DHQC_ENABLE;
OSPIHandle.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED; //>>HAL_OSPI_DELAY_BLOCK_USED;
OSPIHandle.Init.ChipSelectBoundary = 0;
OSPIHandle.Init.MaxTran = 0;
OSPIHandle.Init.Refresh = 400;

if (HAL_OSPI_Init(&OSPIHandle) != HAL_OK)
{
Error_Handler() ;
}


/* Configure the Hyperbus to access memory space -------------------------- */
sHyperbusCfg.RWRecoveryTime = 4;//>>OSPI_HYPERRAM_RW_REC_TIME;
sHyperbusCfg.AccessTime = 6;//>>OSPI_HYPERRAM_LATENCY;
sHyperbusCfg.WriteZeroLatency = HAL_OSPI_LATENCY_ON_WRITE;
sHyperbusCfg.LatencyMode = HAL_OSPI_FIXED_LATENCY;

if (HAL_OSPI_HyperbusCfg(&OSPIHandle, &sHyperbusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
Error_Handler();
}

/* Memory-mapped mode configuration --------------------------------------- */
sCommand.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE;
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
sCommand.Address = 0;
sCommand.NbData = 1;

if (HAL_OSPI_HyperbusCmd(&OSPIHandle, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
Error_Handler();
}

sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;
sMemMappedCfg.TimeOutPeriod = 0x34; /* circa 50 cicli */
if( HAL_OSPI_MemoryMapped(&OSPIHandle, &sMemMappedCfg) != HAL_OK)
{
Error_Handler();
}





And this is the memory test code:

#define DATA_OFFSET 1u

errors = 0;
mod1errors = 0;
uint8_t *pzMem = (uint8_t*) OCTOSPI2_BASE;
uint32_t total_bytes = 64u * 1024u * 1024u;

for (i = 0; i < 100; i++)
{

  for (uint32_t zIndex = 0; zIndex < total_bytes; zIndex += DATA_OFFSET)
  {
     pzMem[zIndex] = (uint8_t) (zIndex & 0xFF);
     __asm("NOP");
  }

  for (uint32_t zIndex = 0; zIndex < total_bytes; zIndex += DATA_OFFSET)
 {
     uint8_t read_val = pzMem[zIndex];
     uint8_t expected_val = (uint8_t) (zIndex & 0xFF);

     if (read_val != expected_val)
     {
          errors++;
     }

     __asm("NOP");
  }

}

if DATA_OFFSET is set to 2 (even byte access -> good)

if DATA_OFFSET is set to 1 (odd/even byte access -> getting errors)

Can anyone help us understand where we're going wrong and how we can get the 64MByte memory to work correctly as well? Thanks in advance

Renato

[KDJEM.1]

Hello @DMast.1 ;

Could you please check ChipSelectBoundary and Refresh values?

Chip select boundary (CSBOUND) configured depending on the memory datasheet. The chip select must go high when crossing the page boundary (2CSBOUND bytes defines the page size).
Refresh rate (REFRESH) required for PSRAMs memories. The chip select must go high each (REFRESH x OCTOSPI clock cycles), configured depending on the memory datasheet.

Thank you.

Kaouthar