Posted on May 17, 2011 at 14:00 
Ok, so to watch 72MHz sysclk signal I must to select in RCC_CFGR.MCO=111 to see PLL clock divided by 2 to see 36MHz, because the maximum speed of GPIO write.
Thks. To answer another question my answer was that it is normal to see 72,70MHz instead 72MHz teorical. Thks to all dudes
