Posted on May 17, 2011 at 14:13RM0008 section 24.3.3 Receiver:
When a character is received
(1) The RXNE bit is set. It indicates that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags).
(2) An interrupt is generated if the RXNEIE bit is set.
(3) The error flags can be set if a frame error, noise or an overrun error has been detected during reception.
(4) In multibuffer, RXNE is set after every byte received and is cleared by the DMA read to the Data Register.
(5) In single buffer mode, clearing the RXNE bit is performed by a software read to the USART_DR register. The RXNE flag can also be cleared by writing a zero to it. The RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun error.
>Is it possible to use DMA for UART data receive and still getting an interrupt on RXNE?
The docs seem to indicate yes. But you still have to test the puppy. (1) & (2) appear to say you will get an interrupt. But (4) might mean that a race condition exists.
For most uses UARTs work well using ISR data transfers. Consider 9600 baud. That is just under one byte per millisecond. I.e. over 72,000 processor clocks per byte. An ISR taking 100 clocks is a insignificant fraction of that. Quadruple that baud rate and it’s still insignificant. One may almost need to use DMA when using UART1 at 4.5M baud. But then you don’t want an interrupt per byte anyway.
Does the IDLE flag work for USART read in DMA mode? Don’t design depending on it without serious checking.
