DCMIPP CSI-2 D-PHY clock CDR never locks

[edenraf]

Hello,

I'm having trouble getting a lock with the DCMI. Lots of information below as required.

Has anyone seen ACTCLF permanently stuck at 0 on STM32N6 despite confirmed HS clock at the input? Are there any additional SNPS D-PHY initialization steps beyond what HAL_DCMIPP_CSI_SetConfig performs. For example, a calibration trigger or an additional register write needed for the clock lane specifically? The SNPS D-PHY databook is not publicly available for STM32N6; if there are clock-CDR-specific internal registers beyond 0xe2/e3/e4 (which appear to be DL0 DDL registers), we have no way to know without that document.

Hardware: STM32N657X0HxQ + Sony 12MP image sensor, 1-lane CSI-2, 1188 Mbps (27 MHz INCK × 44), continuous HS clock mode.

Symptom: The SNPS D-PHY clock CDR never acquires lock.

• CSI_SR1.ACTCLF (bit31) is 0 in every run across many different changes.
• CSI_SR0.SOF0F is always 0.
• CSI_SR1.ERR1/ERR2 over a 2-second capture window are both 0x00.

What IS working (confirmed):

• Sensor is streaming: CSI-2 LANESEL=1-lane confirmed by I2C readback
• HS clock IS physically present at the STM32N6 input: STOPCLF drops to 0 after streaming starts (clock leaves LP-11 so enters HS continuous mode)
• Data lane also exits LP-11: STOPDL1F drops to 0
• ULPS: ULPNCLF=1, ULPNACTF=1 throughout capture window
• Inter-frame LP-11 gaps appear correctly in csi_sr1_or: STOPCLF=1, STOPDL1F=1 during gaps

STM32N6 DCMIPP/D-PHY configuration — all verified:

• PCR = 0x0B: PWRDOWN|CLEN|DL1EN (DL0EN=0 — using inverted lane mapping, physical DL1 is the active lane)
• PFCR = 0x10B3C: HSFR=0x0B (BT_1200 = 1188 Mbps), CCFR=0x3C (32 MHz APB5 clock), DLD=1
• PRCR = 0x02: PEN=1 (PHY enabled)
• LMCFGR = 0x43120100: inverted 1-lane mapping, DL1 active
• DCMIPP->CMCR = 0x1: INSEL=1 (CSI-2 input selected)
• VC0CFGR1 = 0x301: ALLDT=1, CDTFT=3 (RAW10)
• RIMC_ATTRx[8] = 0x310: DCMIPP master secured

SNPS D-PHY internal registers (written while PWRDOWN=0):

• 0xe2 = 0xCC, 0xe3 = 0x01 -> osc_freq_target = 0x01CC = 460 (correct per SNPS table for all bitrates 80–1500 Mbps)
• 0xe4 = 0x19 -> DDL enable + counter
• 0x08 = 0x38 -> deskew polarity
• PTSR is permanently 0x00 in STM32N6 silicon regardless of PHY state - test interface writes cannot be verified by readback

Sensor-side timing registers (I2C readback confirmed):
- All 27 INCKSEL registers correct
- TLPX=0x003F, THS_ZERO=0x009F, TCLK_ZERO=0x014F, HMAX=0x0EF1 - all confirmed

SetConfig timing: Called during inter-frame LP-11 gap (confirmed by init_ulpn_wait_sr1=0x76101000 showing STOPCLF=1|STOPDL1F=1 at call time). init_setconfig_res=0x0 (HAL_OK). PEN=1 fires while clock is in LP-11, so the LP -> HS transition should be available for CDR acquisition. CDR still does not lock.