ADC reading without phase delay

[STuser2]

I have a requirement from customer to read the mains input voltage (down converted to 3.3V) which is 50Hz using ADC and identify the phase delay between the input and after the ADC reading(Ideally it shall be 0 requirement). How to demonstrate? I am using STM32G474RET6. Please guide.  

Edit: I am trying to trigger ADC sample at every 20KHz PWM signal.

[AScha.3]

Zero delay is impossible, the ADC needs 0,25us to convert, so at 50 Hz about 0,0045°.

To "prove" ds is correct, maybe : read ADC and write data direct to DAC , to view output with scope.

But this will add about 1us for data handling , DAC conversion time and settling.

So should show about 0,02° at 50 Hz .

btw

Show this on a dual trace scope, 50Hz -> 20ms, at 2ms/div setting you can see no delay , because 2us delay would show as 0,01mm on screen...not visible. So you can show: no delay (visible). :)

[STuser2]

Only for re confirmation i get the below values

0.0045 and 0.02 Degrees  i get a factor 0.1 less, can you please confirm if i am making any mistake?

[AScha.3]

I just used online calculator...

1us -> 0,02° ....and wrote one zero too few... :)  

Your right.

(corrected now.)