Controller to read wav files from SD CARD

[andrea_mori]

Posted on August 19, 2014 at 15:45

I need a little help to choose the right device.

I would build a digital audio player with the following characteristics:

 - it should read data from SD card only (up to 32GB size)  - SD card will be formatted FAT32  - the root of SD card will contain folders only (named as album title/artist)  - no subfolders will be allowed on SD card  - each SD card folder will contain wav files only (named as title track)  - only 16 bit / 44.1 kHz wav files will be allowed (CD quality)  - music data should be read and managed synchronously  - 6 buttons have to be managed: previous track, next track, play/pause, stop, return and enter to navigate the folders (no buttons using touch screen display)  - TFT display will be managed to show album/artist, title track, time elapsed and so on (replace the buttons if touch)  - data output (16 bit serial X 2 channels) should feed a r-2r discrete ladder DAC  - 74XX595 logic will split the serial data to parallel to feed the ladder network  - master clock should be 11.2896 MHz, shared from both DAC logic and uC, to avoid any divider  - every time a single bit is ready, uC should enable the 595 to store it (595 clock enabled from uC in sync with master clock)  - every time 16 bit for 2 channels are read, uC in sync with master clock should enable the 595s to output parallel data to update the ladder network

 Practically, file system and wav headers aside, using 11.2896 MHz master clock for all the system, I have to start reading 4 bytes from the SD

 card (1 left + 1 right samples), then I should pass each single bit synchronously to 4 * 74XX595.  The clock of the 595 to store data should be enabled either from the master clock and the uC (data ready to store).  After the 32th bit is stored in the last 595, uC should enable the master clock to tell all the 595s to output parallel data to update the ladder network.  Finally the clock of all the 595s should be stopped for 224 cycles, and no data should be read from the SD card.  Now the program has to read next 4 bytes, until the end of the wav file.  In the meantime I have to manage the TFT display and interrupt from the user buttons or touch screen

What device do you suggest to do all the above job? STM32 M4?

 Can I run all the system at the same master clock (11.2896 MHz)?  Can I read and manage data synchronously from the SD card? . Thanks Andrea

[Tesla DeLorean]

Posted on August 19, 2014 at 16:28

What device do you suggest to do all the above job? STM32 M4? Can I run all the system at the same master clock (11.2896 MHz)? Can I read and manage data synchronously from the SD card?

I'd probably opt for an STM32F407 or 429? You could probably do the task with an F1, but the PLL and pin control is more flexible on the F4's Yes, you can run the entire system for a 11.2896 MHz crystal, though this might forclose the use of USB, but you don't specify that as a requirement. Not sure you'd need to read the SD ''synchronously'', at least wrt the audio, the interface is clearly clocked/synchronous in nature. You'd read large block pairs in to ping-pong buffers, at significantly higher rates than the audio leaving, and you wouldn't be reading 4 bytes at a time, you'd ideally pull 32 KB, or at least the cluster size is, aligned to a cluster/sector boundary.

[andrea_mori]

Posted on August 21, 2014 at 15:50

My first problem is to define the right architecture of the system, since I have no experience with uC.

I would design a system rather than a dac or an SD card transport. The reason is that I'm worried about the jitter of an asynchronous system, where transport and Dac are different devices with their own master clock. So, I would place the master clock of the entire system close to the DAC. In other words, I would pull data from the uC output (SPI?), rather than push the data from the uC. In this way I have a precise clock right to the DAC, and I'm sure each bit is latched correctly. Using 11.2896 MHz master clock, the DAC should pull the bits at that frequency from the uC, then when 32 bits are latched I have to tell the DAC to update (44.1 kHz, that means WS for I2S and LRCK fro simultaneous mode). Is that possible? Is the SPI bus the right way to pull data?

[Tesla DeLorean]

Posted on August 21, 2014 at 18:46

Yeah, I think you're confused. The only thing that needs to be tied to the audio output rate, is the audio data you are sending to the DAC. Data from the SD Card can be read much more rapidly and buffered, the audio output will be a continuous stream.

[andrea_mori]

Posted on August 23, 2014 at 13:14

Hi Clive,

thanks for the reply,

I understood what you said, but I have a few questions.

To get precision clock, I have to replace the onboard 8 MHz HSE with mine 11.2896 MHz. I believe I have to desolder the 8 MHz crystal and a pair of capacitors, I'm not sure since I have no schematics of the Disco board

I need a couple of timers: the DAC supports 6.4 MHz maximum bit clock, so the first timer should divide by 2 the master clock frequency. This clock should be stopped after the 16 bit for each channel in simultaneous mode (2 lines) are passed to the DAC. The second timer should divide the master clock by 256 to get 44.1 kHz to update the DAC (sample rate). Can the cpu run at higher frequency using the PLL and the timers run at master clock frequency (external clock)? In other words, can the timers run in background starting from crystal frequency and output directly a GPIO, while the cpu works via the PLL? With the DAC, since it need two lines for data in simultaneous mode (left and right simultaneously), I believe I cannot use the SPI interface with a single data line. Can I use other GPIO or what else?

Thanks

Andrea

[Tesla DeLorean]

Posted on August 23, 2014 at 14:01

The schematics are readily available in the user manuals for the DISCO boards, you should download/review.

You should be able to get a continuous HSE/2 signal out via MCO (PA8) A 22.5792 MHz or 45.1584 MHz might also be worth considering if you can't use the PLL/VCO as a source. SPI is going to clock via an APB clock, at least in master mode. You'd have to look at SPI/I2S modes, and codec options. Triggering DMA/SPI at 44.1 KHz via a TIM should not be a problem.