Clarification Needed on PA14‑BOOT0 (SWCLK / BOOT0) pin functionality in STM32G030C8T6

[Arjun_Vasudevan]

• We are using STM32G030C8T6 (LQFP48 package) in a new design and need clarification regarding pin 36: PA14‑BOOT0, which according to the datasheet serves both:
• SWCLK (Serial Wire Debug clock)
• BOOT0 (boot mode selection)
• In our earlier designs using similar STM32 devices, BOOT0 and SWCLK were separate pins. BOOT0 was typically pulled down, and SWCLK required no external pull.
• However, in the STM32G030 series, BOOT0 is multiplexed on PA14, which is also SWCLK. The datasheet states that upon reset, PA14 is configured as SWCLK with an internal pull‑down enabled.

We would like clarity on the following points:

1. Is an external pull‑down resistor required on PA14‑BOOT0, or is the internal pull‑down on PA14 sufficient for all conditions?
2. Will adding an external pull‑down interfere with SWCLK operation during debugging?
3. Are there recommended application notes or hardware guidelines specific to STM32G0‑series devices where BOOT0 is multiplexed with SWCLK?

[TDK]

The documentation says there is an internal pulldown present and the official ST boards do not have an external pulldown on this pin. It is safe to omit it.

Also note that nBOOT_SEL = 1 by default on this chip which means the BOOT0 pin isn't even sampled. With default settings, the chip always boots to user flash unless it's empty.