Changing the itnvec_start address

[IWahe.1]

Hello everyone,

we are using STM32F072RB for our hardware. The application is linked to stm32f0 library. In the application, we wanted to change the icf file and let the ROM region as well as the interrupt vector table to begin from 0x080a'0000 rather than the standard 0x0800'0000. However this resulted in the application being not able to find the interrupt handlers. Once I set back the interupt vector table back to 0x0800'0000 it works again.

Is there a setting in IAR or in the register that needs to be made such that the interupt vector table couöd be shifted. Thank you very much.

[Pavel A.]

> Is there a setting in IAR or in the register that needs to be made such that the interupt vector table couöd be shifted.

Discussed many times in this forum, please search.

STM32F0 does not have such register (VTOR). Only newer STM32s (CM0+ based ) have this register.

So your program always must have at least two first vectors (stack pointer & start address) at 0x08000000.

Later in runtime you can map the internal SRAM to address 0 and copy the vector table to start of the SRAM.

Actually the vector table always is at 0, but by default 0 is aliased to the internal flash at 0x08000000.

[IWahe.1]

Thank you. Do yu know that what could be missing as the MEM_MODE of SYSCFG->CFGR1 remains at 0x0 after the command:

RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Remap SRAM at 0x00000000 */
SYSCFG_MemoryRemapConfig(SYSCFG_MemoryRemap_SRAM);

What could I be possibly missing?

[Pavel A.]

Maybe you haven't copied enough code from example. Please check again.

[Tesla DeLorean]

Enable the APB2 clock, not reset it.  This is a copy-n-paste of a broken code example. The F0 is a CM0 part the, L0 is a CM0+ supporting the SCB->VTOR register. This is usually set up in SystemInit(), you could use linker symbols for the vector table instead of #defines, this would allow you to just modify the linker script to change the base expectations.