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Bug in HAL_SPI Library HAL_SPI_Transmit

thehavoc
Associate
Posted on July 28, 2016 at 17:20

I found bug in HAL SPI Library.

MCU: STM32L476VGT6 (L476 Discovery board)

CubeMX 4.1

CubeL4 v1.5.1

In transmiting data in 8-bit mode:

/* Transmit data in 8 Bit mode */

else

{

while (hspi->TxXferCount > 0)

{

/* Wait until TXE flag is set to send data */

if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)

{

if(hspi->TxXferCount > 1)

{

/* write on the data register in packing mode */

hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);

hspi->pTxBuffPtr += sizeof(uint16_t);//sizeof(uint8_t);

hspi->TxXferCount -= 2;//hspi->TxXferCount --;

}

else

{

*((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);

hspi->TxXferCount--;

}

}

..

..

}

Where

should contact

to this error fixed?

#hal-spi-bug

2 REPLIES 2
slimen
Senior
Posted on July 29, 2016 at 11:08

Hi,

There is no issue with this code, following the

http://www.st.com/content/ccc/resource/technical/document/reference_manual/02/35/09/0c/4f/f7/40/03/DM00083560.pdf/files/DM00083560.pdf/jcr:content/translations/en.DM00083560.pdf

 in ''Data packing'' paragraph (page 1302):

as Data Register is 16bit (DR),  IP is able to compute two data (2* 8bits) to a 16bits Data packet. 

In case of 8bits data buffer, data are sent by packet of 16bits (2 datas). 

In case of odd data buffer, the last data is sent with an 8bits packet.

Regards

Geoffrey1
Associate III
Posted on August 03, 2016 at 18:43

It isn't technically a bug, because the Cortex processors can handle non-aligned accesses, but it is a perfect example of a totally pointless ''optimization''.  I challenge anyone to demonstrate that it actually speeds up the data transfer and it certainly obfuscates the meaning of the code.

There is an actual bug in the receive code since it transmits garbage (actually whatever happens to be in the receive buffer) which is almost never the right thing to do.