Posted on September 28, 2012 at 00:13
Hi, first of all thanks for reading this!
This is assembly code (gnu arm) for setting up the ST32F103 to make sound out the DAC. It works in 48mhz PLL mode, but not in What follows is the complete program, demonstrating the problem. Thanks again, -Peter B, RTOS engineer, shbobo.net
.thumb
.syntax unified
.equ STACKINIT, 0x2000C000
.equ RCC_CR, 0x40021000
.equ RCC_CFGR, 0x40021004
.equ RCC_APB1ENR, 0x4002101C
.equ GPIOA_CRL, 0x40010800
.equ DAC_BOUNDARY, 0x40007400
.equ DAC_DHR12R1, 0x40007408
@for ST32F103RCT6, uses pin PA4 (DAC)
@compiled with arm-elf-as or arm-linux-gnueabi-as
@-mcpu=cortex-m3 upload with ST-LINK_CLI.exe
@>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
@the following program sets up an external crystal
@at 8 megahertz, then sets up the PLL to multiply.
@it thus works at 48 megahertz (*6), and produces a saw
@waveform at the DAC output, done by the loop at the end.
@this is a distillation of a much larger program that at 48mhz,
@works with USB, adc, timer, dac, SYstick, and GPIO.
@but not at 72 mhz.
@the question is, if you comment out the following equate,
@why does it break at 72 megahertz (*9)???? please,
@comment/uncomment the next line about ''FORTYEIGHT''
.equ FORTYEIGHT, 1
vectors:
.word STACKINIT
.word initiate + 1
.word initiate + 1
.word initiate + 1
.word initiate + 1
.word initiate + 1
.word initiate + 1
.macro LODESTRA reg, val
ldr r1, =\reg @for setting
ldr r0, =\val @configurations
str r0, [r1] @in Mister ST
.endm
initiate:
LODESTRA RCC_CR, 0x00010081 @ HSEON
CRYSTAL_waiter:
ldr r1, = RCC_CR
ldr r1, [r1]
ldr r0, = 0x00020002 @ HSERDY
tst r1, r0
beq CRYSTAL_waiter
@NOTE THE FOLLOWING TWO POSSIBLE CONFIGURATIONS
.ifdef FORTYEIGHT
.equ CLOCKCONFIG, 0x0051FC00
@analyzed in bits:
@xxxx reserved
@x000 MCO off
@x101 USBPRE/1, PLL*6
@0001 PLL*6, HSE as source
@1111 ADC=AHB/8 APB2=AHB/16
@1100 APB1=AHB/2
@0000 0000
.else
.equ CLOCKCONFIG, 0x001DFD00
@analyzed in bits:
@xxxx reserved
@x000 MCO off
@x001 USBPRE/1.5, PLL*9
@1101 PLL*9, HSE as source
@1111 ADC=AHB/8 APB2=AHB/16
@1101 APB1=AHB/4
@0000 0000
.endif
LODESTRA RCC_CFGR, CLOCKCONFIG
LODESTRA RCC_CR, 0x01010081 @PLL ON
PLL_waiter:
ldr r1, = RCC_CR
ldr r1, [r1]
ldr r0, = 0x02020002 @PLL RDY
tst r1, r0
beq PLL_waiter
LODESTRA RCC_CFGR, (CLOCKCONFIG | 2) @ USE PLL as clock
LODESTRA RCC_APB1ENR, 0x20000000 @ DAC APB1 enable
LODESTRA GPIOA_CRL, 0x44004444 @ analog in for DAC
LODESTRA DAC_BOUNDARY, 0x00010001 @ turn on both DACs
1:
ldr r1, = DAC_DHR12R1
strh r0, [r1]
subs r0, r0, 1
b 1b @loop a saw waveform forever!
.end
#pll #pll #!bug #72mhz #pll-72mhz #pll
